M2 Flashcards

1
Q

This transfers the contents of a specific MM

location to the CPU. The word in the MM remains X

A

Fetch or Read.

unchanged.

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2
Q

Read/Fetch Cycle:

A
  1. CPU sends address of the desired location.
  2. MM reads the data stored at that address and sends it to
    the CPU.
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3
Q

This transfers a word of information from
the CPU to a specific MM location. This X the
former contents of that location.

A

Store or Write.

overwrites

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4
Q

Write/Store Cycle:

A

• 1. CPU sends address of the desired location to the
MM, together with the data to be stored into that
location.
• 2. Data is written at desired location.

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5
Q

X accesses a word and a double
word by storing the low-order byte of a word at
the address specified and the high-order byte at
the next location.

A

80x86 family

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6
Q

word consumes X consecutive

memory addresses.

A

two

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7
Q

The 8088 and 80188 microprocessors have an X
bit data bus. This means that the CPU can transfer
X

A

eight

eight bits of data at a time.

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8
Q

Discrete Structures 1
The 8086, 80186, 80286, and
80386sx processors have a X bit
data bus.

A

16

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9
Q

processors that have a 16 bit data bus organize memory into two blanks

A

even bank and

an odd bank

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10
Q

X means that programs
(together with data) are stored in main memory during
execution.

A

Von Neumann Architecture

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11
Q

contains the
memory address of the instruction to be
executed.

A

PC (Program Counter)

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12
Q

holds
the address of the location to or from which
data are to be transferred.

A

MAR (Memory Address Register)

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13
Q

contains
the data to be written or read out of the
addressed location.

A

MDR (Memory Data Register)

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14
Q

contains the

instruction that is being executed.

A

IR (Instruction Register)

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15
Q

On Von Neumann machines like the 80x86, most operations are

A

serialized.

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16
Q

This

means that the computer executes commands in a prescribed order.

A

serialized.

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17
Q

handles all synchronization within a computer system.

A

system clock

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18
Q

is an electrical signal on the control bus which alternates between
zero and one at a periodic rate

A

system clock

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19
Q

The frequency with which the system clock alternates

between zero and one is the system clock frequency.

A

system clock

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20
Q

The time it takes for the system clock to switch from zero to
one and back to zero is the

A

clock period.

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21
Q

One full clock period is

also called a

A

clock cycle.

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22
Q

The clock frequency is simply the X

which occur each second.

A

number of clock cycles

23
Q

is the technical term meaning one cycle per

second.

A

“Hertz” (Hz)

24
Q

is definitely an operation synchronized around the

system clock.

A

Memory access

25
is the amount of time between a memory operation request (read or write) and the time the memory operation completes.
Memory access time
26
Different 80x86 processors have different memory access times ranging X clock cycles
from one to four
27
is nothing more than an extra clock cycle to give some | device time to complete an operation.
wait state
28
n most computer systems there is an additional circuitry between the CPU and memory:
The decoding and buffering logic.
29
are high speed memory elements that resides inside the | Central Processing Unit or CPU.
Registers
30
are used to quickly accept, store, and transfer data and | instructions that are being used immediately by the CPU.
Registers
31
X are the top of the memory hierarchy, and are the fastest way for the system to manipulate data.
registers
32
This register holds the address of | memory where CPU wants to read or write data.
Memory Address Register (MAR):
33
When CPU wants to store some data in the memory or reads the data from the memory, it places the address of the required memory location in the
Memory Address Register (MAR):
34
This register holds the contents of | data or instruction read from, or written in memory.
Memory Buffer Register (MBR):
35
this register is used to store data/instruction coming from the memory or going to the memory
Memory Buffer Register (MBR):
36
is used to specify | the address of a particular I/O device.
I/O Address Register (I/O AR):
37
``` is used for exchanging data between the I/O module and the processor. ```
I/O Buffer Register (I/O BR):
38
is also known as | Instruction Pointer Register.
Program Counter (PC) register
39
This register is used to store the | address of the next instruction to be fetched for execution.
Program Counter (PC) register
40
When the instruction is fetched, the value of IP is incremented. Thus this register always points or holds the address of next instruction to be fetched
Program Counter (PC) register
41
Once an instruction is fetched from main | memory, it is stored in the
Instruction Register. (IR)
42
is located | inside the ALU
Accumulator Register(AC):
43
It is used during arithmetic & logical operations of | ALU.
Accumulator Register(AC):
44
This register holds the initial data to be operated upon, the intermediate results, and the final result of operation.
Accumulator Register(AC):
45
represents a set of memory | blocks
stack
46
is | used to manage the stacks in memory.
Stack Control Register
47
is used to indicate occurrence of | a certain condition during an operation of the CPU.
Flag register
48
t is a special | purpose register with size one byte or two bytes.
Flag register
49
A register used in microcomputers to temporarily store data being transmitted to or from a peripheral device.
Data Register(DR):
50
is an extensive collection of one bit values which | help determine the current state of the processor.
flags register
51
16 bits wide | register, it uses only nine of those bits.
flags register
52
reflect the result of the previous operation | involving the ALU.
Conditional Flags -
53
they control the execution of special functions
Control Flags -