Lesson 9 : Network Components Part 2

Question 1

which controls the flow of information in a multipoint data link system.

Answer 1

Line Control Unit (LCU or LinCo )

Question 2

the primary station, the LCU is often called a _______ because it processes information and serves as an interface between the host computer and all the data communications circuits it serves.

Answer 2

Front-End Processor

Question 3

directs the flow of input and output data between data communications circuits and their respective application programs.

Answer 3

FEP

Question 4

inserted and deleted in the FEP and LCUs

Answer 4

Data-Link Control Character

Question 5

A single special purpose integrated circuit performs many of the fundamental data communications functions and is designed for asynchronous data transmission

Answer 5

Universal Asynchronous Receiver/Transmitter (UART)

Question 6

A single special purpose integrated circuit performs many of the fundamental data communications functions and is designed for synchronous data transmission

Answer 6

Universal Synchronous Receiver/Transmitter (USRT)

Question 7

A single special purpose integrated circuit performs many of the fundamental data communications functions and is designed for asynchronous or synchronous data transmission

Answer 7

Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

Question 8

DIP

Answer 8

Dual in-line Package

Question 9

USARTs are available in __- to __-pin dual in-line packages

Answer 9

24 to 64

Question 10

DTE

Answer 10

Data Terminal Equipment

Question 11

DCE

Answer 11

Data Communications Equipment

Question 12

Special purpose UART chip manufactured by Motorola

Answer 12

Asynchronous Communications Interface Adapter (ACIA)

Question 13

allows UART to operate virtually independently of one another

Answer 13

Bidirectional Data Bus

Question 14

coordinates data transfer between
the line-control unit and the modem

Answer 14

CPU

Question 15

responsible for programming the UART’s
control register, reading the status register,
transferring parallel data to and from the
UART transmit and receive buffer register

Answer 15

CPU

Question 16

specifies the number of data bits per character

Answer 16

Control Word

Question 17

only bit in the UART that is not
optional or programmable.

Answer 17

Start Bit

Question 18

an n-bit data register that
keeps track of the status of the UARTs
transmit and receive buffer registers

Answer 18

Word Register

Question 19

transmit shift register has been completed
transmission of a data character

Answer 19

Transmit Buffer Empty (TBMT)

Question 20

set when a received character has a parity error in it

Answer 20

Receive Parity Error (RPE)

Question 21

set when a character is received without any or with an improper number of stop bits

Answer 21

Receive Framing Error (RFE)

Question 22

set when a character in the receive buffer register is written over by another receive character because the CPU failed to service an active condition on REA before the next character was received from the receive shift register.

Answer 22

Receiver Overrun (ROR)

Question 23

data character has been received and loaded into the receive data register.

Answer 23

Receive Data Available (RDA)

Question 24

CRS

Answer 24

Control-Register Strobe

Question 25

internal to the UART, tells the transmit buffer register when the transmit shift register is empty and available

Answer 25

Transmit End-Of-Character (TEOC) Signal

Question 26

where data picks up the appropriate start, stop, and parity bits.

Answer 26

Steering Logic Circuit

Question 27

TSO

Answer 27

Transmit Serial Output

Question 28

TCP

Answer 28

Transmit Clock

Question 29

set when the character is transferred in parallel into the receive buffer register

Answer 29

Receive Data Available (RDA) Flag

Question 30

RDE

Answer 30

Receive Data Enable

Question 31

detect valid start bits, which indicate the beginning of a data character

Answer 31

Start-bit Verification Circuit

Question 32

can be sometimes interpreted as start bit

Answer 32

Noise Hit

Question 33

difference in time between the beginning of a start bit and when it is detected

Answer 33

Detection Error

Question 34

equal to the time of one receive clock cycle (𝑡𝑐𝑙 = 1/𝑅𝑐𝐿 )

Answer 34

Maximum Detection Error

Question 35

helps reduce clock slippage

Answer 35

Stop Bits

Question 36

Other term for clock slippage

Answer 36

clock skew

Question 37

used for synchronous transmission of data between a DTE and a DCE.

Answer 37

USRT

Question 38

coordinates the flow of data, control signals, and timing information between the DTE and the DCE

Answer 38

Serial Interface

Question 39

What year did the Electronics Industries Association (EIA) created RS-232 specifications

Answer 39

1962

Question 40

created to standardize interface equipment between data terminal equipment and data communications equipment

Answer 40

RS-232 specification

Question 41

What does RS in RS-232 mean?

Answer 41

Recommended Standard

Question 42

its specification identify the mechanical, electrical, functional, and procedural description for the interface between DTEs and DCEs.

Answer 42

RS-232 specification

Question 43

Official name of RS-232

Answer 43

Interface Between Data Terminal Equipment and Data Communications Equipment Employing Serial Binary Data Interchange

Question 44

sometimes referred to as the EIA-232 standard

Answer 44

RS-232D

Question 45

Specifies a cable with two connectors

Answer 45

Mechanical Specification

Question 46

used for transporting asynchronous data between DTE and a DCE when the DCE is connected directly to a standard two-wire telephone line attached to the public switched telephone network

Answer 46

EIA – 561 Modular Connector

Question 47

convert the internal voltage level from the DTE and DCE to RS-232 values

Answer 47

Voltage-leveling Circuits

Question 48

called to a voltage leveler if it outputs signals onto the cable and a terminator if it accepts signals from the cable.

Answer 48

Driver

Question 49

difference in the voltage levels between the driver output and the terminator input

Answer 49

Noise Margin

Question 50

reduces susceptibility to interface caused by noise transients induced into the cable

Answer 50

Noise Margin

Question 51

the minimum noise margin of 2V.

Answer 51

Implied Noise Margin

Question 52

noise margin of the circuit is a high value

Answer 52

High Noise Immunity

Question 53

noise margin is a low value

Answer 53

Low Noise Immunity

Question 54

signals propagate in both directions

Answer 54

Bidirectional