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Data Comm > Lesson 9 : Network Components Part 2 > Flashcards

Lesson 9 : Network Components Part 2 Flashcards

1
Q

which controls the flow of information in a multipoint data link system.

A

Line Control Unit (LCU or LinCo )

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2
Q

the primary station, the LCU is often called a _______ because it processes information and serves as an interface between the host computer and all the data communications circuits it serves.

A

Front-End Processor

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3
Q

directs the flow of input and output data between data communications circuits and their respective application programs.

A

FEP

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4
Q

inserted and deleted in the FEP and LCUs

A

Data-Link Control Character

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5
Q

A single special purpose integrated circuit performs many of the fundamental data communications functions and is designed for asynchronous data transmission

A

Universal Asynchronous Receiver/Transmitter (UART)

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6
Q

A single special purpose integrated circuit performs many of the fundamental data communications functions and is designed for synchronous data transmission

A

Universal Synchronous Receiver/Transmitter (USRT)

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7
Q

A single special purpose integrated circuit performs many of the fundamental data communications functions and is designed for asynchronous or synchronous data transmission

A

Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

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8
Q

DIP

A

Dual in-line Package

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9
Q

USARTs are available in __- to __-pin dual in-line packages

A

24 to 64

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10
Q

DTE

A

Data Terminal Equipment

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11
Q

DCE

A

Data Communications Equipment

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12
Q

Special purpose UART chip manufactured by Motorola

A

Asynchronous Communications Interface Adapter (ACIA)

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13
Q

allows UART to operate virtually independently of one another

A

Bidirectional Data Bus

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14
Q

coordinates data transfer between
the line-control unit and the modem

A

CPU

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15
Q

responsible for programming the UART’s
control register, reading the status register,
transferring parallel data to and from the
UART transmit and receive buffer register

A

CPU

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16
Q

specifies the number of data bits per character

A

Control Word

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17
Q

only bit in the UART that is not
optional or programmable.

A

Start Bit

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18
Q

an n-bit data register that
keeps track of the status of the UARTs
transmit and receive buffer registers

A

Word Register

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19
Q

transmit shift register has been completed
transmission of a data character

A

Transmit Buffer Empty (TBMT)

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20
Q

set when a received character has a parity error in it

A

Receive Parity Error (RPE)

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21
Q

set when a character is received without any or with an improper number of stop bits

A

Receive Framing Error (RFE)

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22
Q

set when a character in the receive buffer register is written over by another receive character because the CPU failed to service an active condition on REA before the next character was received from the receive shift register.

A

Receiver Overrun (ROR)

23
Q

data character has been received and loaded into the receive data register.

A

Receive Data Available (RDA)

24
Q

CRS

A

Control-Register Strobe

25
Q

internal to the UART, tells the transmit buffer register when the transmit shift register is empty and available

A

Transmit End-Of-Character (TEOC)
Signal

26
Q

where data picks up the appropriate start, stop, and parity bits.

A

Steering Logic Circuit

27
Q

TSO

A

Transmit Serial Output

28
Q

TCP

A

Transmit Clock

29
Q

set when the character is transferred in parallel into the receive buffer register

A

Receive Data Available (RDA) Flag

30
Q

RDE

A

Receive Data Enable

31
Q

detect valid start bits, which indicate the beginning of a data character

A

Start-bit Verification Circuit

32
Q

can be sometimes interpreted as start bit

A

Noise Hit

33
Q

difference in time between the beginning of a start bit and when it is detected

A

Detection Error

34
Q

equal to the time of one receive clock cycle (𝑑𝑐𝑙 = 1/𝑅𝑐𝐿 )

A

Maximum Detection Error

35
Q

helps reduce clock slippage

A

Stop Bits

36
Q

Other term for clock slippage

A

clock skew

37
Q

used for synchronous transmission of data
between a DTE and a DCE.

A

USRT

38
Q

coordinates the flow of data, control signals, and timing information between the DTE and the DCE

A

Serial Interface

39
Q

What year did the Electronics Industries Association (EIA) created RS-232 specifications

A

1962

40
Q

created to standardize interface equipment between data terminal equipment and data communications equipment

A

RS-232 specification

41
Q

What does RS in RS-232 mean?

A

Recommended Standard

42
Q

its specification identify the mechanical,
electrical, functional, and procedural description for the interface between DTEs
and DCEs.

A

RS-232 specification

43
Q

Official name of RS-232

A

Interface Between Data Terminal Equipment and Data Communications Equipment Employing Serial Binary Data Interchange

44
Q

sometimes referred to as the EIA-232 standard

A

RS-232D

45
Q

Specifies a cable with two connectors

A

Mechanical Specification

46
Q

used for transporting asynchronous data between DTE and a DCE when the DCE is
connected directly to a standard two-wire
telephone line attached to the public
switched telephone network

A

EIA – 561 Modular Connector

47
Q

convert the internal voltage level from the DTE and DCE to RS-232 values

A

Voltage-leveling Circuits

48
Q

called to a voltage leveler if it outputs signals onto the cable and a terminator if it accepts signals from the cable.

A

Driver

49
Q

difference in the voltage levels between the driver output and the terminator input

A

Noise Margin

50
Q

reduces susceptibility to interface caused
by noise transients induced into the cable

A

Noise Margin

51
Q

the minimum noise margin of 2V.

A

Implied Noise Margin

52
Q

noise margin of the circuit is a high value

A

High Noise Immunity

53
Q

noise margin is a low value

A

Low Noise Immunity

54
Q

signals propagate in both directions

A

Bidirectional

Data Comm (16 decks)

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