Lecture 10 - Power and wrap up Flashcards

1
Q

What is the formula of power, given energy and time?

A

Power = Energy / Time
Watt = Joule / Sec

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2
Q

What is the definition of power

A

Power is the rate of which energy is consumed.

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3
Q

Should you optimize for power or energy?

A

Depends on the system we are designing.
If we are dependent on keeping the system below a temperature to avoid it breaking down, f.example PC or large data centers. Power is important to optimize for, as increased power consumption generates more heat.

In this case, energy is not that important as it is always available. Though it can lead to bigger cost.

For hand held devices, energy is a concern. This is because we have limited energy in form of for example limited battery life. If we minimize energy consumption, we can extend the battery life of the device.

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4
Q

How can a NMOS transistor act as a switch?

A

. Drain
Gate Body
Source

If the value at the gate is 1, the transistor is closed(ON) and the current can flow between the DRAIN and the SOURCE of the transistor.

The switch is OFF(open) when the gate-value is 0, and there cannot flow a current between the source and drain of the transistor.

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5
Q

What is a PMOS transistor

A

The opposite of NMOS.
On when a 0 is supplied at the GATE. Off when a 1 is supplied.

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6
Q

How can you build a CMOS Invertor?

A

. Vdd
. PMOS
V_in. V_out
NMOS

Combine PMOS and a NMOS transistor.

Connect one of their two terminals (DRAIN, SOURCE)

Combine their GATE inputs and take the output from their connected terminals.

When Vin is 0, the PMOS is ON and the curcuit will flow from Vdd to Vout.
When Vin is 1, the NMOS will be on and the value from Voud will be discharged through the NMOS and there will be a logical 0 at the output.

This means that a 0 at input gives 1 at out, and 1 at in gives 0 at out.

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7
Q

How is power consumed in a CMOS Invertor?

A

When in is 0 or 1 there are no path between Vdd and ground, so no power is consumed, meaning in steady state, there is no power consumption.

Power is only consumed during input/output transitions.

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8
Q

What is dynamic power?

A

Power consumption by circuit while doing something useful.

Calculated by:

Power = afC(Vdd)²

a: activity factor (how often is input changed)
f: frequency
C: Capacitance
Vdd: Supply voltage

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9
Q

What is static power?

A

Power consumed by circuit while doing nothing.

This consumption is caused by transistors leaking even when they are in off state.
Ideally, a current will flow between SOURCE and DRAIN when there is a channel between them. But when the device is so small, just a few nano meters, even without a channel, electrons can pass through. This causes an current to occur called Sub-threshold Leakage current.

What should stop the current is an insulator between the s and d, but when the transistors are so small, so are these. Therefor there will also be come electrons moving from the Gate down to the body of the transistor. This is a current called a gate leakage current.

There is also a current between the drain and the body called a junction leakage.

P_static = Vdd * I_static

I_Static: The currents that are flowing

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10
Q

Does static or dynamic power dominate in a circuit?

A

Depends on the technology nodes.

High technology nodes, the leakage power forms a very small portion.

Leakage grow with technology scaling.

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11
Q

How can you prevent leakage?

A

Use materials that are less prone to leakage

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12
Q

What hardware techniques can be used to reduce power consumption?

A

Clock gating
Power gating

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13
Q

What software techniques can be used to reduce power consumption?

A

Sleep modes
Dynamic voltage and frequency scaling (DVFS)

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14
Q

What is clock gating?

A

Circuits typically only change state when the clock is active - rising/falling edge of clock.

Idea: When a circuit is not in use, turn off the clock

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15
Q

How can circuit clocks be turned off

A

Instead of providing the clocksignal directly to a flip flop, pass it through an ANDgate with an enable signal.

This creates a frequency of the power equation to 0. The dynamic power therefor becomes 0

P = afC*Vdd²

Clock gating does not reduce static power, as static power is independant on clock frequency.

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16
Q

What is power gating?

A

Used to avoid static (and dynamic) consumption.

Idea: Turn off power supply when circuit is not in use.

Use a sleep signal. When sleep signal is 1 for a PMOS device, the device is off.

Sleep transistors are usually made with high technology nodes, as these has lower leakage

17
Q

What overhead does power gating result in?

A

Area overhead: Needs extra transistors - sleep transistors

Energy overhead: Sleep transistors needs to be turned on and off. Sleep signal must be created and distributed.

Performance overhead: Sleep unit must be charged and stable for a little while before it can be used.

Power gating should therefore only be implemented when we know it will not be used in a sufficient amount of time. Power saving must be more than the overhead.

18
Q

How can OS power management be used as a software way to reduce power consumption?

A

The OS controls the power consumption of the system by using multiple power modes that are supplied by the hardware.

What modes to choose from is dependent on for example:
- how much activity is happening
- whether we are likely to miss deadlines

To save power, the OS can use sleep modes to provide saving. These are similar to power gating,only they are controlled by the OS.
There is an overhead from entering and exiting sleep modes.

There might be multiple levels of sleep modesproviding different trade offs between overhead and savings.

19
Q

What is dynamic voltage and frequency scaling?

A

OS can choose among multiple frequencies and voltages.

Reducing frequency and voltage reduces dynamic power

20
Q

Is energy affected by reducing frequency?

A

If execution time stays the same, and the frequency is lower, then energy is being saved.
If execution time doubles and power consumption halves, the energy stays the same.

21
Q

Name something that is effected by power consumption?

A

Heat generation

22
Q

Name something that is effected by energy usage?

A

Battery life

23
Q

What is a CMOS circuit?

A

Complimentary metal oxide semiconductor

24
Q

What are the two mechanisms of power consumption in CMOS circuits

A

Dynamic: The logic uses most of its power when changing its output value. If inputs and outputs stays unchanged, dynamic power is not consumed.

Static: Leakage, Transistors draws current even when they’re off. Removed only by turning off power supply

25
Q

What are some ways to reduce power consumption?

A

Reducing voltage

Reducing clock frequency (same energy, less power)

Disabling internal units that are not needed for execution (lowers energy consumption)

Disconnect components, if possible, to remove leakage

26
Q

What are the two possible power management modes?

A

Static- and dynamic management mode

27
Q

What is static management mechanism?

A

It is invoked by the user, but does not depend on other CPU activities.

Example: Power-down mode to save energy

28
Q

What does a power down mode do?

A

Provides high-level way to reduce power consumption, by saving energy.

Mode is entered with an instruction, and cannot be exited by execution of another instruction.

Power mode can end by receiving interrupts or entering of a different event

Entering and exiting power down mode takes energy and time, so to be useful it should be applied for a longer period of time.

29
Q

What is dynamic management mechanism?

A

Takes action to control power consumption based on dynamic activity on PC.

Example:
CPU can turn off sections of the CPU that aren’t in use by the current instruction

30
Q

What does stand by mode do?

A

Continues to supply power to core, but stops or gates most of the processor’s clocks.
The core can be woken up by an external interrupt

31
Q

How can CPU modes be modeled?

A

Using a power state machine.

Each state in machine represent a different mode.

Every state is labeled with its avarage power consumption

The power machine also tracks state-transitions and the time needed to go from one state to another.

32
Q

What is DVFS?

A

Dynamic Voltage Frequency Scaling

Optimizes dynamic power usage by scaling down the voltage to the lowest level that still provides the required performance. Also scales down clock speed based on command setting from software

33
Q

What is race-to-dark (race-to-sleep)

A

Minimize static power consumption.

If leakage is high, the best thing is to run as fast as possible (high frequency) and then shut down CPU

34
Q

What is the formula for total energy consumed?

A

dynamic + static

Static: roughly constant
Dynamic: Depend on clock rate

35
Q

What is important to think about before deciding on using mode changes?

A

Energy and time is also used when changing states.
If the change takes a long time, the energy wasted during change might greater than the energy saved from the mode change.