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Embedded Software > Instruction Sets and Processors > Flashcards

Instruction Sets and Processors Flashcards

1
Q

What is the basic setup of von Neumann architecture?

A

memory and a CPU with registers for PC, IR, and general purpose registers

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2
Q

What is the basic setup of Harvard architecture?

A

data memory, program memory and a CPU with registers for PC, IR, and general purpose registers

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3
Q

What is the main difference between von Neumann and Harvard architectures?

A

harvard can’t use self-modifying code, von Neumann can, Harvard allows 2 simultaneous memory fetches, von Neumann doesn’t, Harvard has greater and more predictable memory bandwidth

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4
Q

What is RISC?

A

reduced instruction set computer, allows load/store, piplinable instructions

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5
Q

What is CISC?

A

complex instruction set computer, many addressing modes and operations

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6
Q

What are the characteristics of instruction sets?

A

fixed vs. variable length, addressing modes, number of operands, and types of operands

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7
Q

What is the programming model?

A

The registers visible to the programmer

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8
Q

What is an example of a register that is not visible to the programmer?

A

Instruction register (IR)

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9
Q

What are some characteristics that can vary between architecture implementations?

A

clock speeds, bus widths, cache sizes

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10
Q

True or false: all assembly languages are not one-to-one?

A

false

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11
Q

What are some basic features of an assembly language?

A

one instruction per line, labels provide names for addresses, instructions are in later columns, and columns run to end of line

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12
Q

What are pseudo-ops?

A

assembler directives that don’t correspond directly to instructions

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13
Q

What can pseudo ops usually do?

A

define current address, reserve storage, hold constants

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14
Q

True or false: there are many versions of the ARM architecture/assembly language?

A

true

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15
Q

What is the meaning if the N flag is logical one for both logical instructions and arithmetic instructions?

A

logical: no meaning, arithmetic: bit 31 is 1 meaning it is a neg number

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16
Q

What is the meaning if the Z flag is logical one for both logical instructions and arithmetic instructions?

A

logical: result is all zeroes, arithmetic: result of op was zero

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17
Q

What is the meaning if the C flag is logical one for both logical instructions and arithmetic instructions?

A

logical: after shift op, ‘1’ was left in carry flag, arithmetic: result is > 32 bits

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18
Q

What is the meaning if the V flag is logical one for both logical instructions and arithmetic instructions?

A

logical: no meaning, arithmetic: result is > 31 bits, possible corruption of signed bit

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19
Q

What is endianness?

A

relationship between bit and byte/word ordering

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20
Q

How is little endian set up?

A

Bit 31 is MSB, Byte 3 is MSByte

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21
Q

How is big endian set up?

A

Bit 31 is MSB, Byte 0 is MSByte

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22
Q

How big is a word in ARM?

A

32-bits

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23
Q

How many bytes can a word be divided into?

A

4 8-bit bytes

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24
Q

How long can ARM addresses be?

A

32-bits

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25
Q

What does Address refer to?

A

byte

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26
Q

True or false: ARM is always big endian?

A

false, endianness can be set up at power-up

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27
Q

What does ADD/ADC do?

A

add/add with carry ex: ADD r0, r2, #3 (r0=r2+3)

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28
Q

What does SUB/SBC do?

A

subtract/subtract with carry ex: SUB r3, r4, r1 (r3=r4-r1)

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29
Q

What does RSB/RSC do?

A

reverse subtract/reverse subtract with carry ex: RSC r3, r4, r1 (r3=r1-r4)

30
Q

What does MUL/MLA do?

A

multiply/multiply and accumulate ex:
MUL r0, r1, r2, r3 (r0=r1*r2+r3)

31
Q

What do AND, ORR, and EOR do?

A

bitwise AND, OR and XOR

32
Q

What does BIC do?

A

bit clear

33
Q

What does LSL/LSR do?

A

logical shift left/right (fills with zeroes) ex: LSL r0, r0, #10

34
Q

What does ASL/ASR do?

A

arithmetic shift left/right (fills with ones) ex: ASR r0, r0, #10

35
Q

What does ROR do?

A

rotate right ex: ROR r0, r0, #2

36
Q

What does RRX do?

A

rotate right extended with C (33 bit rotate including the C bit) ex: RRX r0, r0

37
Q

What does CMP do?

A

compare ex: CMP r1, #3 (does r1-3 and sets condition flags NZCV, does not save arithmetic result)

38
Q

What does CMN do?

A

negated compare ex: CMN r1, #3 (does r1+3 and sets condition flags NZCV, does not save arithmetic result)

39
Q

What does TST do?

A

bit-wise test (AND) (only sets NZCV flags doesn’t save result) ex: TST r1, r2 (r1 & r2)

40
Q

What does TEQ do?

A

bit-wise negated test (XOR) (only sets NZCV flags doesn’t save result) ex: TEQ r1, r2 (r1 XOR r2)

41
Q

What does MOV do?

A

move ex: MOV r1, r0 sets r1 to r0

42
Q

What does MVN do?

A

bitwise NOT ex: MVN r0, r1 does a bitwise NOT of r1 and places it in r0

43
Q

What do LDR, LDRH, and LDRB do?

A

load (half-word, byte) ex: LDR r0, [r1] loads the value stored at the memory address in r1 into r0

44
Q

What do STR, STRH, and STRB do?

A

store (half-word, byte) ex: STR r0, [r1] storess the value in r0 to the memory location of the address stored in r1

45
Q

True or false: You can refer to an address directly in an instruction.

A

false

46
Q

What does ADR do?

A

retrieves the adress specified by the label and stores it in the register ex: ADR r0, FOO

47
Q

What is the difference between ARM and C55x architecture?

A

ARM is load/store architecture, C55x is accumulator architecture

48
Q

What is the difference between ARM and C55x language?

A

C55x is an algebraic assembly language

49
Q

What are some key parts of C55x assembly language?

A

there are intrinsic functions like int_sadd which performs saturating addition

50
Q

What kind of data types does C55x have?

A

word (16 bits) and longword (32 bits)

51
Q

True or false: C55x instructions never operate on register bits?

A

false, some instructions do

52
Q

Fill in the blank: Most registers in C55x are _________.

A

memory-mapped

53
Q

How can you refer to registers in the C55x assembly language?

A

mnemonic name, memory address

54
Q

What are some extra counters that the C55x architecture has?

A

in addition to the PC there is also the XPC (program counter extension(allows for multiple pages to run code at once)) and RETA (subroutine return address)

55
Q

What are some other special features of C55x architecture?

A

there’s 4 40-bit accumulators, and multiple status registers

56
Q

What is the SP?

A

keeps track of user stack pointer

57
Q

What is the SSP?

A

keeps track of the system stack pointer

58
Q

What is SPH?

A

extended data page pointer for both SP and SSP

59
Q

What is a prominent auxiliary register in C55x?

A

CDP for coefficients for polynomial evaluation instructions

60
Q

Which registers are used for circular buffer operations?

A

BK47, AR4-7

61
Q

What are block repeat registers useful for?

A

for looping and repeating certain blocks of code

62
Q

What are the 3 addressing modes of C55x?

A

absolute addressing, direct addressing, indirect addressing

63
Q

What is absolute addressing?

A

supplying an address in the instruction

64
Q

What is direct addressing?

A

using an offset

65
Q

What is indirect addressing?

A

using a register as a pointer

66
Q

What are 2 stacks of C55x?

A

data and system

67
Q

How many different stack configurations does C55x have?

A

3

68
Q

Which stack configuration has independent data and system stacks?

A

Dual 16-bit stack

69
Q

What is the difference between fast and slow return for the dual 16-bit stacks

A

slow return does not use RETA and CFCT while fast does

70
Q

Which stack configuration modifies SP and SSP by the same amount?

A

32-bit stack with slow return

71
Q

What are some tips for efficient loops?

A

no function calls, small loop body, use unsigned int for loop counter, use <= to test LC, make use of compiler (global optimization, software pipelining)

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