CPU Flashcards
1
Q
What is the UART?
A
universal asynchronous receiver transmitter, it provides serial communication
2
Q
What is a the typical type of interface from I/O device to CPU?
A
digital
3
Q
How many functions are integrated into the standard PC interface chip?
A
8251
4
Q
What are serial communication parameters?
A
baud rate, number of bits per character, parity/no parity, even/odd parity, length of stop bit
5
Q
What types of instructions can support I/O?
A
special purpose I/O instructions and memory-mapped load/store instructions
6
Q
Which chip provides in, out instructions?
A
Intel x86
7
Q
What kind of instructions do most CPUs use?
A
memory-mapped
8
Q
Do I/O instructions preclude memory-mapped I/O?
A
no
9
Q
Why is busy/wait very inefficient?
A
the CPU can’t do other work while testing the device and it’s hard to do simultaneous I/O
10
Q
How do you efficiently check the status of I/O device?
A
interrupts
11
Q
What does the interrupt do?
A
allows a device to change the flow control in the CPU and causes a subroutine call to the handle device
12
Q
What does the interrupt force?
A
a subroutine call as the next instruction
13
Q
When interrupt is triggered, how does the CPU know where to go back after the ‘subroutine call’?
A
the return address is saved that way it can go back to the foreground program once the subroutine call is done
14
Q
How are the CPU and the device connected?
A
through a CPU bus
15
Q
What is the CPU and device handshake?
A
device asserts interrupt request and CPU asserts interrupt acknowledge when it can handle interrupt
16
Q
What is a priority?
A
determines which interrupt runs first
17
Q
What is a vector?
A
determines what code is called for each type of interrupt (table of pointers to the interrupt handlers)
18
Q
What is masking?
A
when an interrupt with lower priority than the current one is not recognized until the current interrupt is complete
19
Q
What is the interrupt with highest priority that can never be masked called?
A
non-maskable priority
20
Q
What is a non-maskable priority often used for?
A
power-down
21
Q
What is the interrupt sequence?
A
CPU acknowledges a request, device sends vector, CPU calls handler, software processes request, CPU restores state to foreground program
22
Q
What are some sources of interrupt overhead
A
handler execution time, interrupt mechanism overhead, register save/restore, pipeline-related penalties, cache-related penalties
23
Q
What 2 types of interrupt does ARM7 support?
A
fast interrupt requests (FIQs), and interrupt requests (IQs)
24
Q
What location does the interrupt table start at?
A
0
25
What are the CPU actions of the ARM interrupt procedure?
save PC, copy CPSR to SPSR, force bits in CPSR to record interrupt, force PC to vector
26
What are the handler responsibilities of the ARM interrupt procedure?
restore proper PC, restore CSPR from SPSR, clear interrupt disable flags
27
What is the worst case latency to respond to interrupt with ARM?
27 cycles
28
What is the breakdown for the latency in ARM interrupt?
2 cycles for external request synchronization, up to 20 for current instruction, 3 for data abort, and 2 to enter interrupt handling state
29
What it the latency period for C55x interrupt?
between 7 and 13 cycles
30
What are the two styles of interrupt return for C55x?
fast and slow
31
What are the external interrupts for the ATmega2560?
2, 3, 18, 19, 20, 21
32
What additional bit does the ATmega2560 have in the status register?
global interrupt enable bit
33
What is the interrupt vector's relationship to priority in the ATmega2560?
lower vector = higher priority
34
What is one of the reasons for supervisor mode?
You may want to have a protective barrier between programs
35
What can supervisor mode prevent?
Memory corruption
36
Does C55x have a supervisor mode?
No
37
What does supervisor mode manage?
Various programs
38
What instruction do you use to enter supervisor mode?
SWI
39
What is SWI similar to?
Subroutine
40
What does the SWI instruction do?
sets the PC to 0x08, passed argument to supervisor mode code, and saves the CPSR in the SPSR
41
What is an exception?
an internally detected error
42
Fill in the blanks: Exceptions are ______ with instructions but _______.
synchronous, unpredictable
43
True or false: Exceptions are usually prioritized but not vectorized?
false, they are usually both prioritized AND vectorized
44
What is a trap?
a software interrupt that is an exception generated by an instruction
45
What does a trap do?
calls supervisor mode
46
What is a co-processor?
an added function unit that is called by instruction
47
How many designer-selected co-processors does ARM allow?
up to 16
48
Does C55x use co-processors as well?
yes
49
What are often structured as co-processors?
floating-point units
50
What are some available C55x image/video hardware extensions?
DCT(discrete cosine transform)/IDCT, pixel interpolation, and motion estimation
51
Which C55x devices have image/video hardware extensions?
5509 and 5510
52
True or false: Only one memory location is mapped onto one cache entry?
false, many are
53
What can you have caches for?
instructions, data, or unified data and instructions
54
With caches, is memory access time deterministic?
no
55
What is a cache hit?
when a required location is in a cache
56
What is a cache miss?
when a required location is not in cache
57
What is a working set?
set of locations used by program in a time interval
58
What are some types of misses?
compulsory (cold), capacity, and conflict
59
What is a compulsory (cold) miss?
location has never been accessed
60
What is a capacity miss?
working set is too large
61
What is a conflict miss?
multiple locations in a working set map to same cache entry
62
What is the formula for average memory access time?
-tav = h*tcache + (1-h)*tmain
(h=cache hit rate, tcache = cache access time, tmain = main memory access time)
63
What is the formula for average memory access time for a multilevel cache?
-tav = h1*tl1 + h2*tl2 + (1-h2-h1)*tmain
64
What is a replacement policy?
a strategy for choosing which cache entry to throw out to make room for a new memory location
65
What are two popular replacement strategies?
random and least-recently used (LRU)
66
What are some different cache organizations?
fully-associative, direct-mapped, and n-way set-associative
67
What is a fully-associative cache organization?
any memory location can be stored anywhere in the cache (almost never implemented)
68
What is a direct-mapped cache organization?
each memory location maps onto exactly one cache entry
69
What is an N-way set-associative cache organization?
each memory location can go into one of n sets
70
What are some performance benefits of caches?
keeps frequently-accessed locations in fast cache, cache retrieves more than one word at a time, sequential accesses are faster after first access
71
What are some different types of write operations?
write-through and write-back
72
What is a write-through operation?
immediately copy write to main memory (highly consistent)
73
What is a write-back operation?
write to main memory only when location is removed from cache
73
With direct-mapped caches, are conflict misses easy to generate?
yes
73
With direct-mapped caches, is only one location mapped to a cache block?
no, many are
73
What are some example caches from StrongARM?
16KByte, 32-way, 32-byte block instruction, 16 KByte, 32-way, 32-byte block data
73
What kinds of caches do C55x have??
various models have 16KB, 24KB cache
74
What does memory management allow?
programs to move in physical memory during execution and virtual memory
75
What is virtual memory?
memory images kept in secondary storage that are returned to main memory on demand during execution
76
What is a page fault?
request for location not resident in memory
77
What does address translation require?
some sort of register/table to allow arbitrary mappings of logical to physical addresses
78
What are two basic address schemes
segmented and paged
79
Can segmentation and paging be combined?
yes
80
What do large translation tables require?
main memory access
81
What is a TLB?
a cache for address translation
82
Is a TLB typically big or small?
small
83
What are the memory region types in ARM?
section (1Mbyte), large page (64kbytes), and small page (4kbytes)
84
What is an address in ARM marked as?
either section-mapped or page-mapped
85
ARM has a how many level translation scheme?
2
86
What are the elements of CPU performance?
cycle time, CPU pipeline, and memory system
87
What is pipelining?
several instructions are executed simultaneously at different stages of completion
88
What can cause pipeline bubbles?
branches, memory system delays, etc.
89
What do pipeline bubbles do?
reduce utilization
90
What are some performance measures?
latency and throughput
91
What is latency?
the time it takes for an instruction to get through the pipeline
92
What is throughput?
number of instructions per time period
93
How does pipelining affect latency and throughput?
increases throughput without reducing latency
94
ARM 7 has a how many stage pipe?
3
95
What are the stages of the ARM 7 pipeline?
fetch instructions from memory, decode opcode and operands, execute
96
What is a pipeline stall?
when every step cannot be completed in the same amount of time
97
How do bubbles introduced by stall affect latency and throughput?
increase latency and reduce throughput
98
What often introduce stalls?
branches (branch penalty)
99
What may stall time depend on?
whether branch is taken or not
100
What might need to happen during a branching operation with pipelining?
squash instructions that already started executing
101
When does the CPU know what to fetch?
once the condition is evaluated
102
What can increase pipeline efficiency?
a delayed branch mechanism
103
What is a delayed branch mechanism?
requires n instructions to be executed after branch whether branch is executed or not
104
How to calculate t loop?
tinit + N*(tbody + tupdate) + (N-1)*ttest,worse + ttest,best
105
C55x has a how many stage pipeline?
7
106
What are the stages of the C55x pipe?
fetch, decode, address, access1, access2, read stage, execute
107
What does the address stage of the C55x pipe do?
computes data/branch addresses
108
What does the access1 stage of the C55x pipe do?
reads data
109
What does the access2 stage of the C55x pipe do?
finishes data read
110
What does the read stage of the C55x pipe do?
puts operands on internal busses
111
Why does C55x handle pipelining better?
because of the block registers pipelines won't break with loop or branch cases
112
What is a cache miss penalty?
added time due to a cache miss
113
With what are modern CPU's designed to keep in mind?
power consumption
114
What does heat depend on?
power consumption
115
What does battery life depend on?
energy consumption
116
What are some causes of CMOS power consumption?
Voltage drops, toggling, and leakage
117
What is power consumption proportional to?
V^2
118
In regards to toggling what means more power?
more activity
119
How can leakage be eliminated?
by disconnecting power
120
What is a power saving strategy related to voltage drop?
reducing power supply voltage
121
What are some power saving strategies related to toggling?
run at a lower clock frequency and disable function units with control signals when not in use
122
What is a power saving strategy related to leaking?
disconnect parts from power supply when not in use
123
What are some power management styles?
static power management, and dynamic power management
124
Which power management strategy depends on CPU activity?
dynamic power management
125
What are some ways the PowerPC 603 use dynamic power management?
uses static logic, can shut down unused execution units, and cache is organized into subarrays to minimize amount of active circuitry
126
What is an example of static power management?
user-activated power-down mode
127
What are the costs associated with going into a power-down mode?
time and energy
128
What does the CPU determine regarding power-down mode?
if it is worthwhile going into that mode
129
How can we model CPU power states?
with a power state machine
130
What are some power-saving strategies the StrongARM SA-1100 uses?
processor takes 2 supplies (3.3v or 1.5v) and there are 3 power modes
131
What are the 3 power modes of the StrongARM SA-1100?
run, idle, and sleep
132
What does the idle power mode of the StrongARM SA-1100 do?
stops CPU clock with logic still powered
133
What does the sleep power mode of the StrongARM SA-1100 do?
shuts off most chip activity: 3 steps, each about 30 microseconds, wakeup takes >10ms
