CPU Flashcards
What is the UART?
universal asynchronous receiver transmitter, it provides serial communication
What is a the typical type of interface from I/O device to CPU?
digital
How many functions are integrated into the standard PC interface chip?
8251
What are serial communication parameters?
baud rate, number of bits per character, parity/no parity, even/odd parity, length of stop bit
What types of instructions can support I/O?
special purpose I/O instructions and memory-mapped load/store instructions
Which chip provides in, out instructions?
Intel x86
What kind of instructions do most CPUs use?
memory-mapped
Do I/O instructions preclude memory-mapped I/O?
no
Why is busy/wait very inefficient?
the CPU can’t do other work while testing the device and it’s hard to do simultaneous I/O
How do you efficiently check the status of I/O device?
interrupts
What does the interrupt do?
allows a device to change the flow control in the CPU and causes a subroutine call to the handle device
What does the interrupt force?
a subroutine call as the next instruction
When interrupt is triggered, how does the CPU know where to go back after the ‘subroutine call’?
the return address is saved that way it can go back to the foreground program once the subroutine call is done
How are the CPU and the device connected?
through a CPU bus
What is the CPU and device handshake?
device asserts interrupt request and CPU asserts interrupt acknowledge when it can handle interrupt
What is a priority?
determines which interrupt runs first
What is a vector?
determines what code is called for each type of interrupt (table of pointers to the interrupt handlers)
What is masking?
when an interrupt with lower priority than the current one is not recognized until the current interrupt is complete
What is the interrupt with highest priority that can never be masked called?
non-maskable priority
What is a non-maskable priority often used for?
power-down
What is the interrupt sequence?
CPU acknowledges a request, device sends vector, CPU calls handler, software processes request, CPU restores state to foreground program
What are some sources of interrupt overhead
handler execution time, interrupt mechanism overhead, register save/restore, pipeline-related penalties, cache-related penalties
What 2 types of interrupt does ARM7 support?
fast interrupt requests (FIQs), and interrupt requests (IQs)
What location does the interrupt table start at?
0
What are the CPU actions of the ARM interrupt procedure?
save PC, copy CPSR to SPSR, force bits in CPSR to record interrupt, force PC to vector
What are the handler responsibilities of the ARM interrupt procedure?
restore proper PC, restore CSPR from SPSR, clear interrupt disable flags
What is the worst case latency to respond to interrupt with ARM?
27 cycles
What is the breakdown for the latency in ARM interrupt?
2 cycles for external request synchronization, up to 20 for current instruction, 3 for data abort, and 2 to enter interrupt handling state
What it the latency period for C55x interrupt?
between 7 and 13 cycles
What are the two styles of interrupt return for C55x?
fast and slow
What are the external interrupts for the ATmega2560?
2, 3, 18, 19, 20, 21
What additional bit does the ATmega2560 have in the status register?
global interrupt enable bit
What is the interrupt vector’s relationship to priority in the ATmega2560?
lower vector = higher priority
What is one of the reasons for supervisor mode?
You may want to have a protective barrier between programs
What can supervisor mode prevent?
Memory corruption
Does C55x have a supervisor mode?
No
What does supervisor mode manage?
Various programs
What instruction do you use to enter supervisor mode?
SWI
What is SWI similar to?
Subroutine
What does the SWI instruction do?
sets the PC to 0x08, passed argument to supervisor mode code, and saves the CPSR in the SPSR
What is an exception?
an internally detected error
Fill in the blanks: Exceptions are ______ with instructions but _______.
synchronous, unpredictable
True or false: Exceptions are usually prioritized but not vectorized?
false, they are usually both prioritized AND vectorized
What is a trap?
a software interrupt that is an exception generated by an instruction
What does a trap do?
calls supervisor mode
What is a co-processor?
an added function unit that is called by instruction
How many designer-selected co-processors does ARM allow?
up to 16
Does C55x use co-processors as well?
yes
What are often structured as co-processors?
floating-point units
What are some available C55x image/video hardware extensions?
DCT(discrete cosine transform)/IDCT, pixel interpolation, and motion estimation
Which C55x devices have image/video hardware extensions?
5509 and 5510
True or false: Only one memory location is mapped onto one cache entry?
false, many are
What can you have caches for?
instructions, data, or unified data and instructions
With caches, is memory access time deterministic?
no
What is a cache hit?
when a required location is in a cache
What is a cache miss?
when a required location is not in cache
What is a working set?
set of locations used by program in a time interval
What are some types of misses?
compulsory (cold), capacity, and conflict
What is a compulsory (cold) miss?
location has never been accessed
What is a capacity miss?
working set is too large
What is a conflict miss?
multiple locations in a working set map to same cache entry
What is the formula for average memory access time?
-tav = htcache + (1-h)tmain
(h=cache hit rate, tcache = cache access time, tmain = main memory access time)
What is the formula for average memory access time for a multilevel cache?
-tav = h1tl1 + h2tl2 + (1-h2-h1)*tmain
What is a replacement policy?
a strategy for choosing which cache entry to throw out to make room for a new memory location
What are two popular replacement strategies?
random and least-recently used (LRU)
What are some different cache organizations?
fully-associative, direct-mapped, and n-way set-associative
What is a fully-associative cache organization?
any memory location can be stored anywhere in the cache (almost never implemented)
What is a direct-mapped cache organization?
each memory location maps onto exactly one cache entry
What is an N-way set-associative cache organization?
each memory location can go into one of n sets
What are some performance benefits of caches?
keeps frequently-accessed locations in fast cache, cache retrieves more than one word at a time, sequential accesses are faster after first access
What are some different types of write operations?
write-through and write-back
What is a write-through operation?
immediately copy write to main memory (highly consistent)
What is a write-back operation?
write to main memory only when location is removed from cache
With direct-mapped caches, are conflict misses easy to generate?
yes
With direct-mapped caches, is only one location mapped to a cache block?
no, many are
What are some example caches from StrongARM?
16KByte, 32-way, 32-byte block instruction, 16 KByte, 32-way, 32-byte block data
What kinds of caches do C55x have??
various models have 16KB, 24KB cache
What does memory management allow?
programs to move in physical memory during execution and virtual memory
What is virtual memory?
memory images kept in secondary storage that are returned to main memory on demand during execution
What is a page fault?
request for location not resident in memory
What does address translation require?
some sort of register/table to allow arbitrary mappings of logical to physical addresses
What are two basic address schemes
segmented and paged
Can segmentation and paging be combined?
yes
What do large translation tables require?
main memory access
What is a TLB?
a cache for address translation
Is a TLB typically big or small?
small
What are the memory region types in ARM?
section (1Mbyte), large page (64kbytes), and small page (4kbytes)
What is an address in ARM marked as?
either section-mapped or page-mapped
ARM has a how many level translation scheme?
2
What are the elements of CPU performance?
cycle time, CPU pipeline, and memory system
What is pipelining?
several instructions are executed simultaneously at different stages of completion
What can cause pipeline bubbles?
branches, memory system delays, etc.
What do pipeline bubbles do?
reduce utilization
What are some performance measures?
latency and throughput
What is latency?
the time it takes for an instruction to get through the pipeline
What is throughput?
number of instructions per time period
How does pipelining affect latency and throughput?
increases throughput without reducing latency
ARM 7 has a how many stage pipe?
3
What are the stages of the ARM 7 pipeline?
fetch instructions from memory, decode opcode and operands, execute
What is a pipeline stall?
when every step cannot be completed in the same amount of time
How do bubbles introduced by stall affect latency and throughput?
increase latency and reduce throughput
What often introduce stalls?
branches (branch penalty)
What may stall time depend on?
whether branch is taken or not
What might need to happen during a branching operation with pipelining?
squash instructions that already started executing
When does the CPU know what to fetch?
once the condition is evaluated
What can increase pipeline efficiency?
a delayed branch mechanism
What is a delayed branch mechanism?
requires n instructions to be executed after branch whether branch is executed or not
How to calculate t loop?
tinit + N(tbody + tupdate) + (N-1)ttest,worse + ttest,best
C55x has a how many stage pipeline?
7
What are the stages of the C55x pipe?
fetch, decode, address, access1, access2, read stage, execute
What does the address stage of the C55x pipe do?
computes data/branch addresses
What does the access1 stage of the C55x pipe do?
reads data
What does the access2 stage of the C55x pipe do?
finishes data read
What does the read stage of the C55x pipe do?
puts operands on internal busses
Why does C55x handle pipelining better?
because of the block registers pipelines won’t break with loop or branch cases
What is a cache miss penalty?
added time due to a cache miss
With what are modern CPU’s designed to keep in mind?
power consumption
What does heat depend on?
power consumption
What does battery life depend on?
energy consumption
What are some causes of CMOS power consumption?
Voltage drops, toggling, and leakage
What is power consumption proportional to?
V^2
In regards to toggling what means more power?
more activity
How can leakage be eliminated?
by disconnecting power
What is a power saving strategy related to voltage drop?
reducing power supply voltage
What are some power saving strategies related to toggling?
run at a lower clock frequency and disable function units with control signals when not in use
What is a power saving strategy related to leaking?
disconnect parts from power supply when not in use
What are some power management styles?
static power management, and dynamic power management
Which power management strategy depends on CPU activity?
dynamic power management
What are some ways the PowerPC 603 use dynamic power management?
uses static logic, can shut down unused execution units, and cache is organized into subarrays to minimize amount of active circuitry
What is an example of static power management?
user-activated power-down mode
What are the costs associated with going into a power-down mode?
time and energy
What does the CPU determine regarding power-down mode?
if it is worthwhile going into that mode
How can we model CPU power states?
with a power state machine
What are some power-saving strategies the StrongARM SA-1100 uses?
processor takes 2 supplies (3.3v or 1.5v) and there are 3 power modes
What are the 3 power modes of the StrongARM SA-1100?
run, idle, and sleep
What does the idle power mode of the StrongARM SA-1100 do?
stops CPU clock with logic still powered
What does the sleep power mode of the StrongARM SA-1100 do?
shuts off most chip activity: 3 steps, each about 30 microseconds, wakeup takes >10ms
