Bus-Based Computer Systems Flashcards
1
Q
What is the function of a CPU bus?
A
allows memory, CPU, and devices to communicate
2
Q
What is a bus?
A
a set of wires/communication protocol
3
Q
What determines how devices communicate?
A
bus protocol
4
Q
What happens to devices on the bus?
A
they go through a sequence of states
5
Q
What are protocols specified by?
A
state machines
6
Q
How many state machines per actor are there in the protocol?
A
one
7
Q
Can bus protocols contain asynchronous logic?
A
yes
8
Q
What are the steps of the four-cycle handshake?
A
dev 1 raises enquiry, dev 2 responds with acknowledgment, device 2 lowers acknowledgment once it is done, device 1 lowers enquiry
9
Q
What provides synchronization in microprocessor busses?
A
the clock
10
Q
R/W bit is true during what action?
A
reading
11
Q
What is the name of the signal for when the data is ready?
A
Data ready bit
12
Q
Address and data are how many lines?
A
a or n bit bundles of address and data lines (respectively)
13
Q
How is the behavior of a bus most often specified?
A
a timing diagram
14
Q
What are shown on timing diagrams to make sure signals go to the proper values at the proper times?
A
timing constraints
15
Q
What must be provided when the data is ready?
A
Acknowledge
16
Q
What does the data ready signal allow for?
A
the bus to be connected to devices that are slower than the bus
17
Q
What is the wait state?
A
the cycles between the minimum time at which data can be asserted and when it is actually asserted
18
Q
What is the wait state used for?
A
to connect slow, inexpensive memories to buses
19
Q
What is DMA?
A
direct memory access which performs data transfers without executing instructions
20
Q
What device sets up a data transfer?
A
the CPU
21
Q
What does the DMA engine do during a data transfer?
A
fetches and writes data
22
Q
What is a bus master by default?
A
CPU, sets up transfers
23
Q
What must the DMA do to perform its work?
A
become the bus master
24
Q
What is the bus mastership protocol?
A
bus request (DMA controller->CPU) then bus grant (CPU->DMA controller)
25
What is the operation of the DMA?
CPU sets DMA registers for start address and length, status register controls the unit, once DMA is bus master, transfers automatically
26
What do multiple busses allow for?
parallelism
27
What connects two busses?
a bridge
28
What are the two ARM AMBA bus varieties?
AHB and APB
29
What is the performance characteristic of the AHB bus variety?
high-performance
30
What are the cost/performance characteristics of the APB bus variety?
lower-speed, lower cost
31
What can the AHB bus variety support?
pipe-lining, burst transfers, split transactions, multiple bus masters
32
What is one of the key characteristics of the APB bus variety?
all devices are slaves
33
What types of memory is there?
DRAM, SRAM, and flash
34
What can vary with each type of memory?
capacity and width
35
What is DRAM?
dynamic random-access memory, requires refresh since the values inside the memory cells decay over time
36
What is SDRAM?
synchronous dynamic random-access memory, uses clock to improve performance and pipeline memory access
37
What are some current forms of SDRAM?
DDR (double-data rate) like DDR2 or DDR3
38
What is the dominant type of DRAM?
SDRAM
39
What is ROM?
Read only memory
40
What is a dominant form of field programmable ROM?
flash
41
True or false: ROM can only be field-programmable?
false, can be programmed at factory as well
42
What are some characteristics of flash?
electrically erasable, must be block erased, random access, but write/erase is much slower than read
43
What is the flexible type of flash?
NOR
44
What is the dense type of flash?
NAND
45
True or false: flash memory is volatile?
false
46
Can flash memory be programmed in circuit?
yes
47
What is a negative about flash memory?
writing causes wear that eventually destroys the device, lifetime of approximately 1 mil writes
48
What are the types of flash memory?
NAND and NOR
49
Why is NAND the preferred type of flash?
cheaper, faster erase, and sequential access times
50
What is the difference between a timer and a counter?
timer is incremented by a periodic signal and a counter is incremented by and async occasional signal
51
What can cause interrupt with timers and counters?
rollover
52
What is a watchdog timer?
a timer periodically reset by system timer
53
What happens if a watchdog is not reset?
it generates an interrupt to reset the host
54
How do you do digital to analog conversion?
use a resistor tree
55
For an analog to digital conversion how many comparators do you need for N-bits?
2^n
56
What is another way to convert from analog to digital?
dual-slope conversion
57
How does dual-slope conversion eliminates non-linearities?
charging then discharging
58
Why does a switch need to be debounced?
to eliminate mechanical bouncing
59
How does an encoded keyboard work?
array of switches is read by an encoder, N-key rollover remembers multiple key depressions
60
What must a LED use to limit current?
a resistor
61
What kind of input can a 7-segment LCD display use?
parallel or multiplexed
62
What is the dominant form of high-resolution displays?
LCD (liquid crystal display)
63
What are some other types of high-resolution displays?
plasma, OLED
64
What holds the current display contents in a display?
frame buffer
65
What are display contents written and read by?
processor and video (respectively)
66
What is the input device for a touchscreen?
two-dimensional voltmeter
67
What are the two considerations for architecture?
software and hardware
68
What are the considerations for hardware architecture design?
CPU, bus, memory, and I/O devices
69
What are the considerations for software architecture design?
division among people, conceptual organization, performance, testability, maintenance
70
Does the software design affect the hardware design and vice versa?
yes
71
What are evaluation boards?
boards designed by CPU manufacturer that have CPU, memory and some I/O devices and often a prototyping section, can be used to start designing a custom board
72
How can you add logic to a board?
PLDs, FPGAs, and ASICs
73
What is the purpose of a PLD?
provides low/medium density logic
74
What is the purpose of a FPGA?
provides more and higher-level logic
75
What is the purpose of an ASIC?
(application-specific integrated circuit) made for a single purpose
76
What is a platform?
the PC
77
What are the advantages and disadvantages of a PC as a platform?
pros: cheap and easy to get, familiar software environment, cons: requires a lot of hardware resources, not well adapted to real time
78
What are some typical busses in a PC?
PCI (peripheral component interconnect) and USB (universal serial bus)
79
What are some software elements in a PC?
BIOS (low-level system software to implement low-level functions)
80
What is the typical way for embedded software design?
host/target design
81
What is host/target design?
use a host system to prepare software for target system
82
What are some host-based tools?
cross compiler (compiles code on host for target), and cross debugger (displays target state and allows target to be controlled)
83
What is a software debugger?
a monitor program residing on the target that provides basic debugger functions
84
What do we need to be careful about with the program?
it should not destroy debugger program but should be able to recover some in case of damage caused by user code
85
What is a breakpoint?
allows user to stop execution, examine state, and change state
86
How does a breakpoint work from the instruction level?
replaces breakpointed instruction with a subroutine call to the monitor program
87
What are the actions of the breakpoint handler?
save registers, allow user to examine machine, restore system state before returning
88
What is the safest way to execute the breakpointed instruction?
replace it, execute in place, put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint
89
What is an in-circuit emulator?
a specially-instrumented microprocessor that allows you to stop execution, examine CPU state, and modify registers
90
What is a logic analyzer?
an array of low grade oscilloscopes
91
What are the ways to exercise code?
run on: host, target, instruction-level simulator, cycle-accurate simulator, and hardware/software co-simulation environment
92
What makes debugging difficult in real-time code?
bugs can cause non deterministic behavior and may be timing dependent
93
Which elements does the performance depend on?
all: CPU, cache, bus, main memory, I/O device
94
Which components does bandwidth apply to?
memory, bus, CPU fetches
95
What is the bandwidth dependent on?
the clock rate and the width
96
How do you increase the bandwidth?
increase width or clock rate
97
How do you calculate the transfer time?
t (transfer time) = T (transfer cycles) * P (period of one cycle)
98
How do you calculate transfer cycles?
Tbasic(N) = (D+O)*N/W (N=bytes to transfer W=bus width T=#of bus clock cycles P=bus clock period D=data transfer clock cycles O=overhead clock cycles)
99
True or false: Memories of the same size always have the same aspect ratios.
false, can have different
100
Where can you find the memory component access time?
chip data sheet
101
What allow for faster access for successive transfers on the same page?
page modes
102
What can speed things up?
parallelism
103
When does DMA provide parallelism?
if the CPU doesn't need the bus
