Hardware Redundancy Flashcards
BISER Built In Soft Resilient Error
Is composed of 2 FFs (latches operating in Master Slave mode), a c element and a keeper.
Idea of the Razor
Add a shadow latch that operates with a delayed clock to detect timing errors.
Explain razor error recovery by clock gating
When a delay error is detected, the whole pipeline is stalled by one clk cycle. The remaining FFs are updated from the shadow latches.
Clk gating impacts the processor timing.
Explain razor conterflow error correction.
The error detection is evaluated locally. The instruction affected can finish correctly. But pipeline has to be flushed.
Does not affect timing because communication is local.
Multi cycle delay is introduced in case of recovery.
Explain razor voltage control.
Observe the error rate and control the voltage to keep it inside a certain margin.
What are the assumptions in designing a self checking circuit.?
Each fault belongs to an assumed fault set.
Faults occur sequentially
Time between faults is enough to allow all code inputs to be applied for testing.
Explain self checking design based on error correcting codes.
During faulty free operation, the circuit receives inputs only from a subset of I, the input code space I1 and generates outputs from a subset of Y, from the output code space Y1.
Explain the fault secure property of a self checking circuit.
For any fault in the target fault set, the output of the system for a correct input CW is either the correct CW or a non CW.
Explain the self testing property of a self checking circuit.
For any fault in the target fault set, there is at least one in put CW for which the resulting output is a non CW.
What can happen if a circuit is not totally self checking.
There could be a fault that is not detected by any input CW. Multiple faults may accumulate in the system and single fault assumption does not hold any more. Input CWs may be mapped to wrong output CWs.
Basic architecture of Concurrent Error Detection (CED) Schemes
It is based on HW redundancy of output predictor and checker. Predictor predicts certain characteristics of the output. Checker compares the predicted characteristics with the circuits output.
Problem with classical redundancy scheme (duplex system).
HW overhead is high.
Susceptible to common mode failures (error effects both modules in the same way).
Checker needs to be carefully designed.
What is the problem with parity prediction systems and how can this problem be overcome?
Circuit must be designed such that no logic is shared between the convergence cones. This way a fault only affects one output. If outputs are partitioned in different output groups than HW can be shared.
Briefly expalin how Concurrent Error Detection schemes can be designed based on unidirectional error detecting codes.
Fault in the circuit causes an unidirectional error at the output. This is achieved using inverter free logic.
