Fault Models Flashcards

1
Q

What is a fault model?

A

A fault model is an abstraction of a defect occurring during manufacture or in the field.
They differ in the kinds of defects that can be modelled and in their accuracy.

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2
Q

What is a fault.

A

Is an structural change caused by a defect.

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3
Q

What is defect analysis? And why is it used?

A

Maps defects to faulty behaviours. It is used to generate the set of faults for which tests are generated.
It typically analyses the critical areas of a chip(areas where a defect changes the behaviour of a system).

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4
Q

What is a test vector.

A

Is an input pattern which causes the faulty and the faulty free circuit to produce different values.

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5
Q

What is structural testing?

A

Is to use fault models based on the structural information of the circuit for testing.

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6
Q

What is Fault coverage.

And the difference to effective fault coverage.

A

Given the set of test vectors, we can give a quantitative measure of its quality w.r.t. the fault model.
Some faults cannot be detected by any test vector. Effective fault coverage takes them into account.

                                      Detected Faults Fault Coverage =  --------------------------------------------------
                         Total Faults - Undetected Faults
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7
Q

What are the single stuck at fault assumptions

A

The defects modelled are assumed to tie a gate‐level signal to a constant value
Only a single fault occurs in the circuit.

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8
Q

On the switch level, stuck at fault model cannot model accurately faulty behaviour.
Which fault models are used in CMOS transistors?

A

stuck open

stuck short

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9
Q

What is required to test a stuck open fault?

A

Sequence of vectors to trigger changes in the circuit to test them.

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10
Q

What is a transition delay fault?

A

A delay fault results in a delayed arrive of a transition at a flip flop or primary output of a circuit.

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11
Q

What is a path delay fault? Which paths are considered?

A

A path from input to the output propagates a transition with additional delay.
Not possible to consider all paths.
Normally only long path or time critical paths are considered.

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12
Q

How are bridging faults modelled?

A

It is modelled as a new element which ties the two wires together, causing oscillation, asynchronous or undefined behavior.

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