Design for Testability Flashcards
Motivation
Large VLSI are hard to test without testability measures
There are only few I/O pins to apply tests
Sequential circuits Fault simulation and ATPG are hard.
Reduce test cost and improve fault coverage and quality
Idea behind scan design.
Modify FFs and connect them to a shift register.
Fault simulation and test generation are simplified because only the combinational circuit needs to be considered.
Steps of test application using scan design…
1) Put circuit in test mode
2) shift test pattern
3) run circuit in system mode.
4) capture circuits response
5) shift out the response pattern
Scan design is the state of the art technique. It is transparent to the designer but the design must fulfill certain design rules. Which are the two types of scan design?
Full scan design
Partial scan design (trade off between testability and overhead).
What is built in self test (BIST)?
Is a technique which dedicates a small portion of the circuits logic for testing.
Difference between online bist and offline bist.
Online bist test the circuit while chip is being used on the field. Offline is not activated during normal operation.
Explain the subdivisions of online bist.
Concurrent: Test is carried out while the chip is performing its actions. If an error occur it might be corrected or chip is rolled back to a safe state.
Non-concurrent: Test is interleaved with normal function.
Explain the subdivisions of offline bist.
Functional:
refers to testing the chip w.r.t. its functional specification.
Structural:
test the chip using dedicated on chip circuitry.
Goals of structural offline bist:
lower test time
lower test cost
run without external tester (good for maintenance/repair)
gives better resolution for fault detection and diagnosis.
Which are the major components of the bist architecture?
Test pattern generator (LFSR, ROM, compression techniques).
Test Response evaluation. (can be compressed or compacted).
Which is the maximum period of a LFSR with k registers?
2^k -1
all zero state cannot be part of the sequence
For every k>0 there exists a feedback poly such that the resulting lfsr has maximum period.
Response Analysis.
How does Test response analysis TRE characterizes the circuits behaviour(output)?
By signature A few bits must characterize long output sequences (time compaction) -Ones counting -Transitions counting
large number of output bits (space compaction)
- XOR
- CRC related methods (LSFR reminder)
What is aliasing?
Loss of information (faulty response E’ mapped to same value as correct response E).
How to improve Random Pattern Generation?
Changing seeds
Phase shifter - increase distance between linear dependencies.
Changing Polynomials - overcome linear dependencies.
Problem with unknown values in the context of signature.
Can corrupt the signature.
