Data Manipulation Flashcards

1
Q

Computer Architecture

A

Central Processing Unit (CPU) processor
-Arithmetic/Logic unit vs. Control unit
-Registers
+General purpose
+Special purpose
Bus
Motherboard

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2
Q

Machine instruction and machine language

A

Machine instruction : An instruction encoded as a bit pattern recognizable by the CPU
Machine language : The seet of all instructions recognizable by a machine

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3
Q

Machine Language Philosophies

A

RISC : Reduces Instructions Set Computing
-Few, simple, efficint, fast
-PowerPC by IBM/Motorola/Apple/ARM
CISC : Complex ınstruction Set Computing
-Many, convenient, powerful instructions
-Intel

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4
Q

Machine Instruction Types

A

+Data Transfer : Copy data one location to another
+Arithmetic/Logic : Use existing bit patterns to compute new ones
+Control : Direct the execution pf the program

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5
Q

Parts of a Machine Instructions

A

-Op-code : Which operation
-Operand : Gives more detailed info about operation

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6
Q

Program Execution

A

Controlled by two special-purpose registers
-Program counter : address of next instruction
-Instruction register : current instruciton
Machine Cycle
-Fetch
-Decode
-Execute

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7
Q

Special purpose registers

A

Program counter : address of next instruction
Instruction register : current instruction

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8
Q

Machine cycle

A

Fetc Decode Execute

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9
Q

Arithmetic/Logic Operations

A

Logic : OR/XOR/AND
Rotate and Shift
Arithmetic : Add, subtract, multiply, devide

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10
Q

Communicating with other devices

A

+Controller
+Port
+Memory Mapped I/O
+Direct memory access (DMA)
+Von Neumann Bottleneck
+Handshaking
+Parallel Communication
+Serial Communication

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11
Q

Communicating with other devices
+Controller :

A

An intermaediary apparatus that handles communication between the computer and a device
-Specialized controllers for each type of device
-General purpose controllers (USB and FirWire)

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12
Q

Communicating with other devices
+Port :

A

The point at which a device connects to a computer

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13
Q

Communicating with other devices
+Memory Mapped I/O :

A

CPU communicates with peripheral devices as though they were memory cells

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14
Q

Communicating with other devices
+Direct Memory Access (DMA) :

A

Main memory access by a controller over the bus

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15
Q

Communicating with other devices
+Von Neumann Bottleneck :

A

Insufficient bus speed impedes performance

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16
Q

Communicating with other devices
+Handshaking :

A

The process of coordinating the transfer of data between components

17
Q

Communicating with other devices
+Parallel Communication :

A

Several communications paths trasnfer bits simultaneously

18
Q

Communicating with other devices
+Serial Communication :

A

Bits are transferred one after the other pver a single communication path

19
Q

Kbps

A

1,000 bps

20
Q

Mbps

A

1,000,000 bps

21
Q

Gbps

A

1,000,000,000 bps

22
Q

Bandwith :

A

Maximum available rate

23
Q
A