Computer Architecture Flashcards

1
Q

5 registers in Von Neumann architecture

A
Program counter (PC)
Memory address register (MAR)
Memory data register (MDR)
Current instruction register (CIR)
Accumulator (ACC)
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2
Q

ALU

A

Arithmetic Logic Unit

Carries out calculations on data

  1. arithmetic operations: add, subtract
  2. logical operations: AND, OR

Holds temporary values used during calculations in a register called the accumulator (ACC)

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3
Q

Control Unit (CU)

A

contains CIR and PC
Manages the flow of data and interaction between the components of the processor
Signals are generated along the control bus to tell the components of the computer what to do
Reads/fetches instructions from memory

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4
Q

IAS

A

Immediate Access Store

Used to hold data and instructions before they are processed
e.g. registers, RAM, cache

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5
Q

PC

A

Contains the address of the next instruction to be fetched

Increments to point to the address of the next instruction to be fetched

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6
Q

MAR

A

Holds the address(location) of the current instruction/data to be fetched
The contents of the PC are copied here and then transferred along the Address Bus

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7
Q

MDR

A

Temporary storage between the Central Processing (CPU) and primary memory
Contains the instructions/data after it is fetched from main memory

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8
Q

CIR

A

Contains the instructions to be decoded

It is copied from the MDR

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9
Q

ACC

A

Accumulator

Holds data (temporarily) that is currently being used in calculations by the Logic Unit

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10
Q

Address bus

A

Transports the memory address of the next item to be fetched between processor and memory

Data travels one way (unidirectional) from CPU to Memory

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11
Q

Control bus

A

Carries (transports) signals that control the actions of the CPU and that synchronise the fetch-execute cycle

Data can travel one way (unidirectional) or both ways (bidirectional)

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12
Q

Data bus

A

Carries (transports) data that is currently being processed between processor, memory and peripherals

Data travels both ways (bidirectional)

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13
Q

CPU 3 main stages

A

Fetch
Decode
Execute

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14
Q

Von Neumann cycle

A
  1. PC contains the address of the next instruction to be fetched
  2. The address held in the PC is placed on the address bus and copied onto the MAR
  3. The data bus fetches the instructions from main memory using the memory address contained in the MAR and then transfers it to the MDR
  4. The instruction in the MDR is copied to the CIR
  5. The PC is incremented by 1
  6. The instruction is then decoded and executed by the Control Unit
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15
Q

Stored program concept

A
  1. program is stored on secondary storage device
  2. data and instructions are moved to RAM
  3. data and instruction are stored in same memory
  4. data and instructions are moved to registers to be executed
  5. instructions are fetched one at a time and executed one after another
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