CMOS

Question 1

CMOS

Answer 1

complementary metal-oxide
semiconductor

Question 2

is the semiconductor technology used in the transistors that are manufactured into most of today’s computer microchips

Answer 2

CMOS

Question 3

It’s a technology used in the fabrication of integrated circuits (ICs), particularly for digital logic circuits and microprocessors.

Answer 3

CMOS

Question 4

In ________ technology, both kinds of transistors are used in a complementary way to form a ____________ that forms an effective means of __________

Answer 4

CMOS, current gate, electrical control

Question 5

PMOS

Answer 5

P-channel Metal-Oxide-Semiconductor

Question 6

NMOS

Answer 6

N-channel Metal-Oxide-Semiconductor

Question 7

CMOS technology utilizes both ________ and ________ transistors on the same chip.

Answer 7

PMOS and NMOS

Question 8

These transistors are configured in a complementary manner, meaning that one type of transistor is used for the high voltage state (logic 1) and the other type for the low voltage state (logic 0).

Answer 8

PMOS and NMOS

Question 9

The complementary arrangement allows CMOS circuits to have __________power consumption because power is only consumed during transitions between ____________, minimizing ____________ dissipation

Answer 9

very low, logic states, static power

Question 10

The main advantage of CMOS over NMOS and BIPOLAR technology is the much _______power dissipation

Answer 10

smaller

Question 11

Unlike NMOS or BIPOLAR circuits, a “Complementary MOS circuit” has almost ____________power dissipation

Answer 11

no static

Question 12

________ is only dissipated in case the circuit actually switches. This allows the integration of more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.

Answer 12

Power

Question 13

________________ consists of P-channel MOS (PMOS) and N-channel MOS (NMOS).

Answer 13

CMOS transistor

Question 14

low power consumption, high noise immunity, and scalability to smaller feature sizes, which allows for increased integration density and improved performance

Answer 14

CMOS technology

Question 15

is built on a p-type substrate with n-type source and drain diffused on it. The majority of carriers are electrons.

Answer 15

NMOS

Question 16

When a high voltage is applied to the gate, the ________ will conduct

Answer 16

NMOS

Question 17

when a low voltage is applied to the gate, NMOS will __________

Answer 17

not conduct

Question 18

considered to be faster than PMOS, since the carriers in this, which are electrons, travel twice as fast as the holes

Answer 18

NMOS

Question 19

consists of P-type Source and Drain diffused on an N-type substrate.

Answer 19

PMOS

Question 20

The majority of carriers are holes. When a high voltage is applied to the gate, the PMOS will ____________. When a low
voltage is applied to the gate, the PMOS ____________.

Answer 20

not conduct, will conduct

Question 21

The ________ devices are more immune to noise than NMOS devices

Answer 21

PMOS

Question 22

In CMOS technology, both N-type and P type transistors are used to design _________________

CMOS Working Principle

Answer 22

logic functions

Question 23

The same signal which turns ON a transistor of one type is used to ____________ a transistor of the other type

CMOS Working Principle: This characteristic allows the design of logic devices using only simple switches, without the need for a pull-up resistor

Answer 23

turn OFF

Question 24

MOS transistors are electrically __________________

CMOS Working Principle

Answer 24

controlled switches

Question 25

Voltage at gate controls path from ________________ ## Footnote CMOS Working Principle

Answer 25

source to drain

Question 26

Complementary CMOS logic gates (3) ## Footnote CMOS Working Principle

Answer 26

1. NMOS pull-down network 2. PMOS pull-up network 3. static CMOS

Question 27

nMOS: 1 = ____ PMOS: 0 = ____ ## Footnote CMOS Working Principle

Answer 27

ON

Question 28

Series: ________ must be ON Parallel: ________ can be ON ## Footnote CMOS Working Principle

Answer 28

both, either

Question 29

In ________________ a collection of n-type MOSFETs is arranged in a pull-down network between the output and the low voltage power supply rail (Vss or quite often ground). ## Footnote CMOS Working Principle

Answer 29

CMOS logic gates

Question 30

Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of ________________ in a ________ network between the output and the higher voltage rail (often named Vdd). ## Footnote CMOS Working Principle

Answer 30

p-type MOSFETs, pull-up

Question 31

Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be ____ when the n-type MOSFET is ____, and vice-versa. ## Footnote CMOS Working Principle

Answer 31

ON, OFF

Question 32

The ________ are arranged such that one is ON and the other OFF for any input pattern. ## Footnote CMOS Working Principle

Answer 32

networks

Question 33

CMOS offers relatively (1)________, (2)________________, (3)________________ in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed). ## Footnote CMOS Working Principle

Answer 33

1. high speed 2. low power dissipation 3. high noise margins

Question 34

The inverter circuit as shown in the figure below. It consists of PMOS and NMOS FET. The ________ serves as the gate voltage for both transistors. ## Footnote CMOS Inverter

Answer 34

input A

Question 35

The NMOS transistor has input from ____ (ground) and the PMOS transistor has input from _____. ## Footnote CMOS Inverter

Answer 35

Vss, Vdd

Question 36

The terminal Y is output. When a high voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS becomes an ____________, and NMOS switched OFF so the output will be ________ to Vss. ## Footnote CMOS Inverter

Answer 36

open circuit, pulled down

Question 37

When a ____________ (

Answer 37

low-level voltage

Question 38

figure shows a 2-input Complementary MOS NAND gate. It consists of ____________ NMOS transistors between Y and Ground and ____________ PMOS transistors between Y and VDD. ## Footnote CMOS NAND Gate

Answer 38

two series, two parallel

Question 39

If either input A or B is ________, at least one of the NMOS transistors will be ____, breaking the path from ____________. But at least one of the pMOS transistors will be ____, creating a path from ## Footnote CMOS NAND Gate

Answer 39

logic 0, OFF (Y to Ground), ON (Y to VDD)

Question 40

the output Y will be high. If ________ are high, both of the nMOS transistors will be ____ and both of the pMOS transistors will be ____. Hence, the output will be ________. ## Footnote CMOS NAND Gate

Answer 40

both inputs, ON, OFF, logic low

Question 41

A 2-input NOR gate is shown in the figure below. The ____________ are in parallel to pull the output low when either input is high. ## Footnote CMOS NOR Gate

Answer 41

NMOS transistors

Question 42

The ________________ are in series to pull the output high when both inputs are low, as given in the below table. The ________ is never left floating. ## Footnote CMOS NOR Gate

Answer 42

PMOS transistors, output