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ELECS > CMOS > Flashcards

CMOS Flashcards

1
Q

CMOS

A

complementary metal-oxide
semiconductor

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2
Q

is the semiconductor technology used in the transistors that are manufactured into most of today’s computer microchips

A

CMOS

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3
Q

It’s a technology used in the fabrication of integrated circuits (ICs), particularly for digital logic circuits and microprocessors.

A

CMOS

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4
Q

In ________ technology, both kinds of transistors are used in a complementary way to form a ____________ that forms an effective means of __________

A

CMOS, current gate, electrical control

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5
Q

PMOS

A

P-channel Metal-Oxide-Semiconductor

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6
Q

NMOS

A

N-channel Metal-Oxide-Semiconductor

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7
Q

CMOS technology utilizes both ________ and ________ transistors on the same chip.

A

PMOS and NMOS

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8
Q

These transistors are configured in a complementary manner, meaning that one type of transistor is used for the high voltage state (logic 1) and the other type for the low voltage state (logic 0).

A

PMOS and NMOS

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9
Q

The complementary arrangement allows CMOS circuits to have __________power consumption because power is only consumed during transitions between ____________, minimizing ____________ dissipation

A

very low, logic states, static power

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10
Q

The main advantage of CMOS over NMOS and BIPOLAR technology is the much _______power dissipation

A

smaller

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11
Q

Unlike NMOS or BIPOLAR circuits, a “Complementary MOS circuit” has almost ____________power dissipation

A

no static

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12
Q

________ is only dissipated in case the circuit actually switches. This allows the integration of more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.

A

Power

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13
Q

________________ consists of P-channel MOS (PMOS) and N-channel MOS (NMOS).

A

CMOS transistor

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14
Q

low power consumption, high noise immunity, and scalability to smaller feature sizes, which allows for increased integration density and improved performance

A

CMOS technology

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15
Q

is built on a p-type substrate with n-type source and drain diffused on it. The majority of carriers are electrons.

A

NMOS

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16
Q

When a high voltage is applied to the gate, the ________ will conduct

A

NMOS

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17
Q

when a low voltage is applied to the gate, NMOS will __________

A

not conduct

18
Q

considered to be faster than PMOS, since the carriers in this, which are electrons, travel twice as fast as the holes

A

NMOS

19
Q

consists of P-type Source and Drain diffused on an N-type substrate.

A

PMOS

20
Q

The majority of carriers are holes. When a high voltage is applied to the gate, the PMOS will ____________. When a low
voltage is applied to the gate, the PMOS ____________.

A

not conduct, will conduct

21
Q

The ________ devices are more immune to noise than NMOS devices

A

PMOS

22
Q

In CMOS technology, both N-type and P type transistors are used to design _________________

CMOS Working Principle

A

logic functions

23
Q

The same signal which turns ON a transistor of one type is used to ____________ a transistor of the other type

CMOS Working Principle: This characteristic allows the design of logic devices using only simple switches, without the need for a pull-up resistor

A

turn OFF

24
Q

MOS transistors are electrically __________________

CMOS Working Principle

A

controlled switches

25
Q

Voltage at gate controls path from ________________

CMOS Working Principle

A

source to drain

26
Q

Complementary CMOS logic gates (3)

CMOS Working Principle

A
  1. NMOS pull-down network
  2. PMOS pull-up network
  3. static CMOS
27
Q

nMOS: 1 = ____
PMOS: 0 = ____

CMOS Working Principle

A

ON

28
Q

Series: ________ must be ON
Parallel: ________ can be ON

CMOS Working Principle

A

both, either

29
Q

In ________________ a collection of n-type MOSFETs is arranged in a pull-down network between the output and the low voltage power supply rail (Vss or quite often ground).

CMOS Working Principle

A

CMOS logic gates

30
Q

Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of ________________ in a ________ network
between the output and the higher voltage rail (often named Vdd).

CMOS Working Principle

A

p-type MOSFETs, pull-up

31
Q

Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be ____ when the n-type MOSFET is ____, and vice-versa.

CMOS Working Principle

A

ON, OFF

32
Q

The ________ are arranged such that one is ON and the other OFF for any input pattern.

CMOS Working Principle

A

networks

33
Q

CMOS offers relatively (1)________, (2)________________, (3)________________ in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed).

CMOS Working Principle

A
  1. high speed
  2. low power dissipation
  3. high noise margins
34
Q

The inverter circuit as shown in the figure below. It consists of PMOS and NMOS FET. The ________ serves as the gate voltage for both transistors.

CMOS Inverter

A

input A

35
Q

The NMOS transistor has input from ____ (ground) and the PMOS transistor has input from _____.

CMOS Inverter

A

Vss, Vdd

36
Q

The terminal Y is output. When a high voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS becomes an ____________, and NMOS switched OFF so the output will be ________ to Vss.

CMOS Inverter

A

open circuit, pulled down

37
Q

When a ____________ (<Vdd, ~0v) applied to the inverter, the NMOS switched OFF and PMOS switched ON. So the output becomes Vdd or the circuit is pulled up to Vdd.

CMOS Inverter

A

low-level voltage

38
Q

figure shows a 2-input Complementary MOS NAND gate. It consists of ____________ NMOS transistors between Y and Ground and ____________ PMOS transistors between Y and VDD.

CMOS NAND Gate

A

two series, two parallel

39
Q

If either input A or B is ________, at least one of the NMOS transistors will be ____, breaking the path from ____________. But at least one of the pMOS transistors will be ____, creating a path from

CMOS NAND Gate

A

logic 0, OFF (Y to Ground), ON (Y to VDD)

40
Q

the output Y will be high. If ________ are high, both of the nMOS transistors will be ____ and both of the pMOS transistors will be ____. Hence, the output will be ________.

CMOS NAND Gate

A

both inputs, ON, OFF, logic low

41
Q

A 2-input NOR gate is shown in the
figure below. The ____________ are in parallel to pull the output low when either input is high.

CMOS NOR Gate

A

NMOS transistors

42
Q

The ________________ are in series to pull the output high when both inputs are low, as given in the below table. The ________ is never left floating.

CMOS NOR Gate

A

PMOS transistors, output

ELECS (10 decks)

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