3. Machine Level Architecture Flashcards
What is Main memory
All data and instructions stored in main memory
Define processor
Executes programs and supervises the operation of the rest of the system
Define main memory
Data store that can be directly addressed by the CPU
Define RAM
Random access memory Can be read from and written to. Data is cleared when the power is off
Define ROM
Read-only memory Can only be read from. Data is maintained when the power is off
What is in the 3 box model
CPU, Main memory, Input/ Output System bus
What is the system bus
The Control Bus The Address Bus The Data bus
Define address bus
Single directional Carries address signals from the CPU to Main Memory and I/O devices
Define Data Bus
Bi- directional Bus Typically consists of 32 wires Used to transport data between the 3 components
What is the benefit of a larger data bus
The larger the data bus, the more data can be transported at one time. Therefore more complex instructions can be used
Define Control Bus
Bi-directional bus Typically consists of 8 wires. Used to transport control signals between the 3 components.
Define Computer Bus
A set of parallel wires connecting independent components of a computer system
Define I/O
Input / Output Allows the CPU to communicate with peripherals
Define Input Devices
Used to get information into the system - keyboard, mouse, touch screen
Used to send information out of the system -VDU( Visual Display Unit), printer, speakers
Define Output Devices
Define I/O controller
An electronic circuit that connects to a system bus and an I/O device. It provides the correct voltages and currents for the system bus and the I/O device . Keyboard controller, disk controller, video display controller
Define I/O device
A hardware unit that sends or receives data, or stores data by communicating with the processor and main memory through an I/O controller
Define Periperal
A computer device that is not part of the CPU. Can be external - Mouse, Keyboard, Monitor Can be internal - CD drive
Define I/O port
A set of data, command and and status registers. Allows for I/O devices to be connected without the need for special equipment
Define secondary storage
Permanent storage memory not directly connected to the processor
Define Addressable memory
Data blocks in main memory
Define Stored Program Concept
A program must be in Main Memory to be executed. It is processed with fetch, decode, execute one at a time
Define ALU
Arithmetic Logic Unit Does operations such as ADD, SUBTRACT. Performs the arithmetic and logic operations.
Define Program Control Unit
Fetches program instructions from memory, decodes them and executes them, 1 at a time
Define Registers
Fast memory locations inside the processor that may be dedicated or general purpose
Define Clock
A timing device connected to the processor that synchronises the fetch, decode, execute cycle.
Define Clock speed
The number of cycles performed by the CPU per second. Measured in hertz.
What are the 4 registers used in the fetch, decode execute cycle
Program counter Memory address register Memory buffer register Current instruction register
Define Program Counter
An incrementing counter that keeps track of the memory address of which instruction is next
Define Memory Address Register
Holds the address in memory of the next instruction to be executed
Define Memory Buffer Register
A two-way register that holds the data fetched from memory or data waiting to be stored in memory
Define Current Instruction Register
A temporary holding ground for the instruction that has just been fetched from memory
Define General Purpose Register
A register not assigned a specific role. Programmers may use general purpose registers
Define dedicated register
A register assigned a specific role. Programmers may use some, but not all dedicated registers
How can you increase performance
Increase clock speed Adjust word length Increase bus width
Why must clock speed be limited
Heat generated in the chip by higher frequencies can’t be removed quickly enough
Define Word Size
The number of bits of information that a processor can process at one time
Define Bus Size
The number of bits of information a bus can carry at one time The u umber of wires making up the bus
Define Machine Code
Simple instructions that are executed directly by the CPU Binary code
Define Instruction Set
The range of instructions that a CPU can execute
Define EEPROM
Electronically erasable programmable read-only memory. Its contents may be altered but writing is about 100 times slower than reading
Define System Bus
The main highway connecting the processor, main memory and I/O controllers
What are the 2 parts of an instruction
OPCODE OPERAND
Define OPCODE
The instruction name / operation
Define OPERAND
The data or address to perform the instruction on
First step of Fetch Execute cycle
MAR ← [PC]
The contents of the Program Counter, the address of the next instruction to be executed is placed in the Memory Address Register
Second Step of the Fetch Execute Cycle
MBR ← [Memory Addressed]
PC ← [PC + 1]
The Address is sent from the MAR, along the Address Bus to Mian Memory. The Instruction at the adderss is returned along the Data Bus to the Memory Buffer Register.
Simultainiously, the Conents of the Program Counter is increased by 1
Third Step of the Fetch Execute Cycle
CIR ← [MBR]
The MBR loads the Current Instruction Register with the instruction to be executed
Fourth step of the Fetch Execute Cycle
Decode Instruction
Fifth step of the Fetch Execute Cycle
Execute Instruction
Uses registers such as ALU if necessary
