Topic #4: Architecture and Organization

Question 1

What are the two problems encountered with integers?

Answer 1

They can’t express fractions
Range number is limited to the number of bits used

Question 2

What are the three concepts of the Von Neumann Architecture

Answer 2

• Data and instructions are stored in a single read-write memory
• The contents of the memory are addressable by location, without regard to the type of data contained there.
• Execution occurs in a sequential fashion (unless explicitly modified) from one instructon to the next

Question 3

It refers to one address followed by N data cycles

Answer 3

Block Data Transfer

Question 4

The ___ of data bus has an impact on the system performance

Answer 4

Width

Question 5

PCI makes use of centralized ___ arbitration scheme in which each master has a unique request (REQ) and grant (GNT) signal

Answer 5

Synchronous

Question 6

With interrupts, the processor can be engaged in executing other instructions while an _____ is in progress

Answer 6

I/O Operation

Question 7

To accomodate interrupts, an ____ is added to the instruction cycle

Answer 7

Interrupt Cycle

Question 8

In the interrupt cycle, the processor checks to see if any interrupts have occured. If no interrupts are pending, the processor proceeds to the ____ and fetches the next instruction of the current program

Answer 8

Fetch Cycle

Question 9

In the case of ____ address and data buses, the address is put on the address bus and remains there while the data is put on the data bus

Answer 9

Multiplexed

Question 10

The widerr ____ the greater range of location that can be referenced

Answer 10

Address Bus

Question 11

A bus that connects major computer components (processor, memory, I/O) is called a _____

Answer 11

System Bus

Question 12

A key characteristic of a bus is that it is a _____ transmission medium

Answer 12

Shared

Question 13

In addition, the PCI specification defines _____ optional signal lines, divided into the following functional groups: interrupt pins and cache support pins

Answer 13

49

Question 14

A mixture of slow and fast devices, using older and newer technology, can share a bus

Answer 14

Asynchronous timing

Question 15

Bus includes a clock line upon which a clock transmits a regular sequence alternating 1’s and 0’s

Answer 15

Asynchronous timing

Question 16

What is the range of numbbers in a 4-bit unsigned system

Answer 16

0 to 15

Question 17

Address and data information may be transmitted over the same set of lines is an example of this bus type

Answer 17

Multiplexed

Question 18

An interrupt generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions

Answer 18

I/O

Question 19

What are the components of the IEEE Standard for Floating-point Arithmetic

Answer 19

Sign of Mantissa
Biased Component
Normalized Mantissa

Question 20

There are ____ mandatory signals for PCI which are divided into the systems pins and address and data pins

Answer 20

32

Question 21

In the case of a ____ addresss/data bus, the bus is first used for specifying the address and then for transferring the data

Answer 21

Dedicated

Question 22

Execution of a program consists of a set of instructions stored in memory. What are the steps in instruction processing?

Answer 22

1. The processor reads (fetches) instructions from one memory at a time
2. Executes the fetched instruction

Question 23

Virtually all computers provide a mechanism by which other modules (I/O, memory) may _____ the normal processing of the processor

Answer 23

Interrupt

Question 24

The wider ______ the greater the number of bits transferred at one time

Answer 24

Data bus

Question 25

Using PCI, a computer can support both new PCI cards while continuing to support Industry Standard Architecture (ISA) _____ cards, an older standard

Answer 25

Expansion

Question 26

The use of multiple buses, each of which connects only a subset of modules

Answer 26

Physical Dedication

Question 27

An interrupt generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis

Answer 27

Timer

Question 28

An interrupt generated by a failure such as power failure or memory parity error

Answer 28

Hardware failure

Question 29

An interrupt generated by some condition that occurs as a result of an instructon execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, or reference outside a user’s allowed memory space

Answer 29

Program

Question 30

A bus type that makes use of a separate dedicated address and data line

Answer 30

Dedicated