Topic #4: Architecture and Organization Flashcards
What are the two problems encountered with integers?
They can’t express fractions
Range number is limited to the number of bits used
What are the three concepts of the Von Neumann Architecture
- Data and instructions are stored in a single read-write memory
- The contents of the memory are addressable by location, without regard to the type of data contained there.
- Execution occurs in a sequential fashion (unless explicitly modified) from one instructon to the next
It refers to one address followed by N data cycles
Block Data Transfer
The ___ of data bus has an impact on the system performance
Width
PCI makes use of centralized ___ arbitration scheme in which each master has a unique request (REQ) and grant (GNT) signal
Synchronous
With interrupts, the processor can be engaged in executing other instructions while an _____ is in progress
I/O Operation
To accomodate interrupts, an ____ is added to the instruction cycle
Interrupt Cycle
In the interrupt cycle, the processor checks to see if any interrupts have occured. If no interrupts are pending, the processor proceeds to the ____ and fetches the next instruction of the current program
Fetch Cycle
In the case of ____ address and data buses, the address is put on the address bus and remains there while the data is put on the data bus
Multiplexed
The widerr ____ the greater range of location that can be referenced
Address Bus
A bus that connects major computer components (processor, memory, I/O) is called a _____
System Bus
A key characteristic of a bus is that it is a _____ transmission medium
Shared
In addition, the PCI specification defines _____ optional signal lines, divided into the following functional groups: interrupt pins and cache support pins
49
A mixture of slow and fast devices, using older and newer technology, can share a bus
Asynchronous timing
Bus includes a clock line upon which a clock transmits a regular sequence alternating 1’s and 0’s
Asynchronous timing
What is the range of numbbers in a 4-bit unsigned system
0 to 15
Address and data information may be transmitted over the same set of lines is an example of this bus type
Multiplexed
An interrupt generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions
I/O
What are the components of the IEEE Standard for Floating-point Arithmetic
Sign of Mantissa
Biased Component
Normalized Mantissa
There are ____ mandatory signals for PCI which are divided into the systems pins and address and data pins
32
In the case of a ____ addresss/data bus, the bus is first used for specifying the address and then for transferring the data
Dedicated
Execution of a program consists of a set of instructions stored in memory. What are the steps in instruction processing?
- The processor reads (fetches) instructions from one memory at a time
- Executes the fetched instruction
Virtually all computers provide a mechanism by which other modules (I/O, memory) may _____ the normal processing of the processor
Interrupt
The wider ______ the greater the number of bits transferred at one time
Data bus
Using PCI, a computer can support both new PCI cards while continuing to support Industry Standard Architecture (ISA) _____ cards, an older standard
Expansion
The use of multiple buses, each of which connects only a subset of modules
Physical Dedication
An interrupt generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis
Timer
An interrupt generated by a failure such as power failure or memory parity error
Hardware failure
An interrupt generated by some condition that occurs as a result of an instructon execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, or reference outside a user’s allowed memory space
Program
A bus type that makes use of a separate dedicated address and data line
Dedicated
