Architecture and Organization (3) Flashcards
Collectively called the data bus
Data lines
Perform the operation indicated in the instruction
Data Operation
Specify operations to be performed
Command Signlas
If the operation involves reference to an operand in memory or available via I/O, then determin the address of the operand
Operand Address Calculation
Disable interrupts whule ann interupt is being processed
Disabled Interrupt
PCI signal line group that includes the clock and reset pins
System pins
It consists of the significant digits in a scientific notation or floating point number
Normalized Mantissa
Are used to control the access to and the use of the data and address lines
Controle Lines
Efficient way of storing fractions
Floating Point
Employed to hold temporarily the right hand instruction from a word in memory
IBR
Analyze instruction to determine type of operation to be performed and operand/s to be used
Instruction Operating Decoding
Basic Functon performed by a Computer
Execution of a program
Employed to hold temporary operand and results of ALU operations
AC and MQ
Added to the actual exponent in order to get the stored exponent
Biased Exponent
It is simply means that the processor can and will ignore that interrupt request signal
Disabled interrupt
It indicates the validity of data and address information
CC
Contains the 8-bit opcode instruction being executed
IR
PCI signal line group that controls the timing of transactions and provides coordination among initiators and targets
timing signals
These pins are needed to support a memory on PCI that can be cached in the processor or another device
Cache Support Pins
Contains the address of the next instruction-pair to be fetched from memory
PC
These pins are provided for PCI devices that must generate requests for service
Interrupt Pins
He and his colleagues in 1946 began the design of a new stored-program computer at Princeton Institute for Advanced Studies
John Von Neuman
Fetch the operand from memory or read it in from I/O
Operand Fetch
The processing required for a single instruction
Instruction Cycle
A feature of computer systems that allows certain hardware subsystems to access main system memory, independent of the central processing unit
Direct Memory Access
It is a communication pathway connecting two or more devices
Bus
Specifies the address in memory of the word to be written form or red into the MBR
MAR
A computer gets its instructions by reading them from memory, and a program could be set or altered by setting the values of a portion of memory
Stored-Program Concept
PCI signal line group that is used to report parity and other errors
Error Reporting Pins
Read instructions from its memory location into the processor
Instruction Fetch
Defines priorities for interrupt and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be itself interrupted
nested interrupt processing
The prototype of all subsequent general-purpose computers
Von Neumann Machine
PCI signal line group that includes 32 lines that are time multiplexed for addresses and data
Address and data pins
A popular high-bandwidth processor independent bus that can function as a peripheral bus
Peripheral Component Interconnect
Determine the address of the next instruction to be executed
Instruction address calculation
Write the result into memory or out to I/O
Operand Store
Zero represents a positive number and 1 represents a negative number
Sign of mantissa
Contains a word to be stored in memory sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
MBR
Agreed upon standard of the computer industry for the storage of floating numbers
IEEE 754
Are used to designate the source or destination of the data on the data bus
Address Lines
Reads Instructions from the memory location into the processoor
IF
Fetcch the operand from memory or read it in from I/O
OF
Perform the operation indicated in the struction
OS
Analyze instruction to determine type of operation to be performed and operand/s to be used
IAC
If the operation invloves reference to an operand in memory or available via I/O, then determine the address of the operand
OAC
Determine the address of the next instruction to be executed
DO
