Synchronization Flashcards
What is atomic exchange?
EXCH R1, 78(R2) - swaps the two values in R1 and the mem location in 78(R2).
How do you implement a lock with atomic exchange?
R1 = 1
While (R1 == 1) EXCH R1, lockvar
What is the drawback to atomic exchange?
You are constantly writing
Test-and-write impl?
look up
What are the cons of atomic EXCH and test-write?
Since they are performing a load and a store for a single instruction, they are really bad for pipelining => would need to add another memory stage just to deal with atomic instructions
How does a load linked instruction work?
Behaves just like a normal load, plus it stores the address in a link register. Replaces the ‘read’ of an atomic instruction
What does a store conditional instruction work?
- Checks if its computed address is the same as the one in the link register
- If same => normal store, return 1
- Else => return 0 (no store)
How is LL/SC atomic?
Must rely on snooping all writes to lockvar (our load link addr). If we snoop a write, we put 0 in the link register. AKA we rely on coherence to ensure it is atomic
How can LL/SC be used to make small critical sections more efficient?
Can use them instead of a lock, since it is storing a variable atomically
LL, R1, MEM
Load MEM to R1, store MEM in link register
SC R1, MEM
Store R1 to MEM. If success, R1 = 1, else R1 = 0
What is barrier synchronization?
Barrier ensures that all threads must have reached the barrier, before any can leave it.
What is need for a barrier synchronization implementation?
Counter (n threads)
flag (set when counter = n)
Why is a simple barrier implementation not reuseable?
If a core cannot read the flag variable=1 fast enough, another core can reset it back to 0 and the first core will spin indefinitely (and block the other threads too since it will never re-reach the barrier)
How do we implement reusable barriers?
Switch the flag each time (i.e the value that we are waiting for should switch)
