Introduction

Question 1

What are the goals of computer architecture?

Answer 1

To improve performance and to anticipate future trends so that by the time a feature is released, we are not outdated.

Question 2

Moore’s Law

Answer 2

Every 18-24 months, technology advances such that we get twice the amount of transistors on the same chip area

Question 3

What are the implications of Moore’s Law for computer architecture?

Answer 3

Every 18-24 months, we want to:

1. double processor speed (2x transistors)
2. 1/2 the energy requirement (1/2 transistors)
3. Double the memory capacity

Question 4

What is the memory wall?

Answer 4

The gap between how fast our processors’ speeds are improving (2x according to Moore’s law) and how fast our memory access time is growing (1.1x).

Question 5

How do we deal with the memory wall?

Answer 5

Caches!

Question 6

What is dynamic (active) power?

Answer 6

Power consumed by the activity in a circuit

Question 7

What is dynamic power dependent on?

Answer 7

Capacity (chip area), voltage, frequency, and activity factor (how many transistors are active at one time)

Question 8

What must we do in order to keep dynamic power the same with faster chips?

Answer 8

Lower the voltage!

Question 9

What is static power?

Answer 9

Power consumed when the chip is powered on, but idle

Question 10

Why is a lower voltage bad for static power?

Answer 10

A lower voltage causes more power to ‘leak’ when device is idle

Question 11

Explain the relationship between static and dynamic power

Answer 11

Lower voltage == less dynamic power, BUT
Lower voltage == more leakage == higher static power. DP increases with voltage, SP decreases, there is a sweet spot minimum that you want to hit

Question 12

What is fabrication?

Answer 12

The cost of producing a chip

Question 13

How do you produce a chip?

Answer 13

Take a wafer, flatten it out, do a bunch of stuff to it, then cut it up into X amount of chips
All chips that test okay are sold, others are thrown out

Question 14

How to decrease chip cost?

Answer 14

The fabrication cost is mostly constantly, so cut more chips per wafer

Question 15

What is the fabrication yield?

Answer 15

Working chips / chips on wafer

Question 16

How do bad chips affect fabrication yield?

Answer 16

Having bad chips is signification worse for larger chips than for smaller ones

Question 17

How does Moore’s Law affect fabrication yield?

Answer 17

Cost increases dramatically with larger chips size. We can use Moore’s law to 1) have a smaller chip for a much lower cost or 2) keep the same sized chip, and sell a faster chip for the same cost to produce