Cache Coherence

Question 1

What is write-update coherence?

Answer 1

Broadcast writes to other cores and update their caches

Question 2

What is write-invalidate?

Answer 2

invalid other cores’ caches on a write

Question 3

What is cache snooping?

Answer 3

write broadcasts on a shared bus, the order of broadcasts on shared bus is the order the writes are updated in each cache

Question 4

What is directory coherence?

Answer 4

each block is assigned an ‘ordering point’

Question 5

How does snooping ensure read/write order?

Answer 5

Cores must arbitrate broadcasts on the bus

Question 6

How can we reduce reads/writes to memory?

Answer 6

Add a dirty bit, update memory when the block is removed from the cache. A core with a dirty bit set responds to reads from other cores. Only 1 core can have a dirty bit set at a time

Question 7

How do we reduce writes to the bus?

Answer 7

Add shared bit to indicate if this block is stored in other caches. Add an extra bus line to signal if another cache has a block in the cache when another one reads/writes

Question 8

What are the pros/cons of write-invalidate snooping?

Answer 8

(-) always have a miss on a read when other caches write

(+) after a write, all reads/writes are local to that cache until another cache performs a read/write

Question 9

What type of coherence do most modern processors use and why?

Answer 9

Write-invalidate. Write-update has very bad performance when a thread is switched to another core (because it has to keep updating the old addresses)

Question 10

What is the Invalid state?

Answer 10

block is not in the cache or block is in the cache with a valid bit == 0

Question 11

What is the Shared state?

Answer 11

Block is unmodified (may be in 1 or more caches) and contains the same data as memory. block can be read without updating other cores, but must notify other cores if a write occurs

Question 12

What is the modified state?

Answer 12

There are no other copies of this block in other caches and it has changes to it. Can read and write to the block without sending any messages to other cores

Question 13

What are the ways to implement cache-to-cache transfers?

Answer 13

1. Abort/retry - C1 aborts C2’s read request and writes block back to memory. C2 must try again later
2. Intervention - C1 sends intervention signal to memory (“I will respond” and updates memory value). C1 responds to C2 with value
   For modified state!

Question 14

What is the improvement of MOSI over MSI?

Answer 14

MSI and cache-to-cache transfers have a lot of writes to memory, MOSI looks to improve thiis

Question 15

In MSI coherence, when does a cache respond to another cache’s read/write request?

Answer 15

Only during a read in the M state (shared state reads go to memory)

Question 16

What is the owner state and why was it introduced?

Answer 16

Avoids reads/writes to memory when we have the block in one of our caches. Responsible for giving data to other caches and for writing the block back to memory

Question 17

How do you get into the owner state?

Answer 17

When we are in the M state and see a read, we provide the data, but then we switch into O state (avoiding memory access)

Question 18

What is the drawback to MSI/MOSI?

Answer 18

It is less efficient for thread-private data. When we write, must send 2 bus signals (get data, put in M state)

Question 19

What is the exclusive state?

Answer 19

Don’t need to send reads/writes to the bus. But once we write, we put in M state (without sending to bus)

Question 20

What advantage does directory based coherence provide?

Answer 20

It scales better. The bus traffic needed for snooping becomes too large after 16 cores. Directory coherence is not broadcast based, so there is less contention

Question 21

Describe directory coherence

Answer 21

The directory is distributed across all the cores, with each core responsible for a different set of blocks. Each core must keep track of the state and which blocks have the data in a non-invalidated state

Question 22

What is a dirty bit in directory coherence?

Answer 22

Block is not necessarily dirty, if cache has exclusive access, then it can update the block without notifying the directory, so block will be marked as dirty in the directory

Question 23

How does a cache get a block in directory coherence?

Answer 23

Sends a request to the home slice. Directory sends data and state that the cache should be in

Question 24

What are the types of coherence misses?

Answer 24

False and true sharing. True sharing (two cores access the same data). False sharing (two cores access different data that is in the same block)