Structure and function of the processor

Question 1

define hardware

Answer 1

the physical components which make up a computer system

Question 2

define register

Answer 2

an area of very fast memory inside the CPU itself which temporarily stores small amounts of binary data

all arithmetic, logical, or shift operations take place in registers

Question 2

define CPU

Answer 2

central processing unit
has a number of different components which enable it to carry out its task of executing instructions

Question 3

define motherboard

Answer 3

the main system board which connects all the hardware components

Question 3

define register exam answer

Answer 3

• temporary storage/memory location
• inside the CPU
• used for a single specific purpose
• faster access speed than RAM/secondary storage

Question 4

what is the purpose of the control unit (CU)?

Answer 4

direct the operations of the CPU:
- controlling and coordinating the activities of the CPU
- managing the flow of data between the CPU and other devices
- accepting the next instruction
- decoding instructions
- storing the resulting data back in memory

Question 5

what is the purpose of the arithmetic logic unit (ALU)?

Answer 5

completes all of the arithmetical and logical operations.

A: all mathematical operations such as addition and subtraction on fixed or floating point numbers

L: boolean logic operations such as AND, OR, NOT, and XOR

also, shift operations on bits

Question 5

what is the purpose of the program counter (PC)?

Answer 5

holds the address of the next instruction to be executed

Question 6

what is the purpose of the accumulator (ACC)?

Answer 6

temporary storage for data being processed during calculations/stores the result

• for I/O in processor, it acts as a buffer (holds data that is on its way to somewhere else)/gateway

Question 7

what is the purpose of the memory address register (MAR)?

Answer 7

holds the address of a location that is to be read from or written to

Question 8

what is the purpose of the memory data register (MDR)?

Answer 8

temporarily stores data that has been read or data that needs to be written

• acts as a buffer (memory designed to hold data that is on its way to somewhere else)

Question 9

what is the purpose of the current instruction register (CIR)?

Answer 9

holds the current instruction being executed, divided up into operand and opcode

Question 9

what is the width of a bus?

Answer 9

the number of parallel wires the bus has.

the width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time

buses are typically 8, 16, 32 or 64 wires wide

Question 10

define bus

Answer 10

a set of parallel wires which connect two or more components inside the CPU
- data bus
- address bus
- control bus
^collectively called system bus

Question 11

what is the data bus?

Answer 11

a bi-directional bus used for transporting data and instructions between components

Question 11

what is the control bus?

Answer 11

a bi-directional bus used to transmit control signals between internal and external components.

its purpose is to transmit command, timing and specific status information between system components

Question 11

what is the address bus?

Answer 11

the bus used to transmit the memory addresses specifying where data is to be sent to or retrieved from.

the width of the address bus is proportional to the number of addressable memory locations

Question 12

what are the control lines?

Answer 12

determine the direction of data flow, and when each device can access the bus

Question 12

what is assembly language?

Answer 12

uses mnemonics to represent instructions - a simplified way of representing machine code.

the instruction is divided into operand and opcode in the CIR

Question 13

what is the opcode?

Answer 13

specifies the type of instruction to be executed

Question 14

what is the operand?

Answer 14

contains the data or the address of the data upon which the operation is to be performed.

Question 15

what is the fetch-decode-execute cycle?

Answer 15

the sequence of operations that are completed to execute an instruction

Question 16

what is involved in the fetch phase?

Answer 16

• The address of the next instruction is copied from the PC to the MAR
• instruction held at that address is copied to MDR by the data bus
• simultaneously, the contents of the PC is incremented
• the value held in the MDR is copied to the CIR

Question 17

what is involved in the decode phase?

Answer 17

the contents of the CIR are split into operand and opcode

opcode is used to determine the type of instruction and what hardware to use to execute it

operand holds either:
- actual data to be operated on
- address of data to be used within the operation

Question 18

what is involved in the execution phase?

Answer 18

the appropriate instruction/opcode is carried out on the operand

Question 19

what is pipelining?

Answer 19

the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously, holding appropriate data in a buffer near the CPU until it’s required. while one instruction is being fetched, the previous could be decoded and the one before that, executed.

aims to reduce the amount of the CPU which is kept idle.

Question 20

what can pipelining be separated into?

Answer 20

instruction pipelining and arithmetic pipelining

instruction pipelining is separating out the instruction into fetching, decoding, and executing

arithmetic pipelining is breaking down the arithmetic operations and overlapping them as they are performed

Question 21

what is the pipelining exam answer?

Answer 21

• concurrent processing of multiple instructions
• one instruction can be fetched while the previous is being decoded…
• …and the one before is being executed
• in the case of a branch, the pipeline is flushed
• increases the speed of execution

Question 22

what problems can arise from pipelining?

Answer 22

when branch or jump instructions occur:
- could be followed by one of two possible instructions; which will only be determined at execution
- this means the wrong one may be fetched/decoded while using pipelining