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Computer Science Paper 1 > Structure and Function of the Processor > Flashcards

Structure and Function of the Processor Flashcards

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1
Q

What is inside the CPU (Central Processing Unit )

A
  • ALU (Arithmetic Logic Unit)
  • Registers
  • Control Unit
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2
Q

What does the Arithmetic Logic Unit (ALU) do

A

Completes all the arithmetical and logical operations

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3
Q

Name the different Control Units and their function

A
  • PC (Program Counter) - holds the address of the next instruction to be executed by the processor
  • ACC (Accumulator) - stores the results from calculations
  • MAR (Memory Address Register) - temporarily holds the address of the memory location that the processor needs to access
  • MDR (Memory Data Register) - temporarily holds the data that the processor needs to access
  • CIR (Current Instruction Register) - holds the current instruction that the processor is executing divided into opcode and operand
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4
Q

What are the functions of the Control Unit

A
  • Directing the operations inside of the CPU
  • Decodes instructions
  • Sends control signals to coordinate movement of data through the processor / execute instruction
  • Controls buses
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5
Q

Describe two ways in which the accumulator is used

A
  • Temporary storage during calculations.
  • I/O in processor and is used as a buffer.
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6
Q

What are registers

A

Small memory cells inside of the CPU that operate at high speeds and temporarily store data

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7
Q

What is a bus

A

A set of parallel wires which connect two or more components inside the CPU

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8
Q

What is the width of a bus

A

The number of parallel wires it has, this is directly proportional to the number of bits that can be transferred simultaneously at any given time

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9
Q

What are the three buses inside the CPU

A
  • Address Bus
  • Data Bus
  • Control Bus
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10
Q

Describe the function of the three buses

A
  • Address Bus - transmits the memory addresses between components
  • Data Bus - bi-directional bus that transmits data and instructions between components
  • Control Bus - bi-directional bus that transmit control signals between components
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11
Q

What is the system bus

A

The collection of the data bus, address bus and control bus

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12
Q

What is the width of the address bus proportional to

A

The number of addressable memory locations

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13
Q

What does adding a wire to the address bus do to the number of addressable locations

A

It doubles the number of addressable locations

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14
Q

Describe the different control signals and their functions

A
  • Bus request - shows that a device is requesting the use of the data bus
  • Bus grant - shows that the CPU has granted access to the data bus
  • Memory write - data is written into the addressed location using this bus
  • Memory read - data is read from a specific location to be placed onto the data bus
  • Interrupt request - shows that a device is requesting access to the CPU
  • Clock - used to synchronise operations
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15
Q

What is Assembly Language

A
  • A low level language that uses mneomincs to represent instructions
  • The instruction is divided up into operand and opcode
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16
Q

What is Opcode

A

Specifies the instruction to be performed and the memory location

17
Q

What is Operand

A

Holds a value related to the data on which the instruction is to be performed

18
Q

What is the main function of a CPU

A

Fetch, Decode, Execute

19
Q

Describe what happens during a Fetch

A
  • Contents of PC are copied into MAR
  • MAR is sent along the address bus to RAM
  • The Control unit instructs a memory read operation to allow the contents of the memory location to be transferred
  • The data now stored in RAM is placed and sent along the data bus
  • The Data Bus loads the Instructions into MDR
  • The contents of the MDR are copied into the CIR
  • Finally, the control units increments the PC by 1
20
Q

Describe what happens during a Decode

A

The contents of the CIR is split into operand and opcode

21
Q

Describe what happens during a Execute

A

The opcode is executed on the data

22
Q

What are the three factors that affect the performance of the CPU

A
  • Clock Speed
  • Number of Cores
  • Size of Cache
23
Q

How does the clock speed function

A
  • Clock speed is determined by the system clock
  • All processor activities begin on a clock pulse
  • Each CPU operation starts as the clock changed from 0 to 1
24
Q

What is a core within a computer

A
  • A core is an independent processor that is able to execute its own fetch-execute cycle
  • A computer with multiple cores can complete more than one fetch-execute cycle at any given time
  • However, some programs aren’t optimised for the use of more than one core
25
Q

What is cache memory

A
  • The CPU’s onboard memory which can be acessed a lot faster than main memory
  • Instructions fetched from main memory are copied to the cache, so if required again it can be accessed quicker
  • As cache fills up, unused instructions get replaced
26
Q

Describe the 3 Levels of Cache

A
  • Level 1 Cache - Very fast memory cells with a small capacity
  • Level 2 Cache - Relatively fast memory cell, with a medium sized capacity
  • Level 3 Cache - Much larger and slower memory cell
27
Q

What is Pipelining

A
  • When Processes are arranged in a series, the output of one process is the input of next
  • The process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously which increases the speed of execution
28
Q

Give two examples of where pipelining is used in any computer system

A
  • Instruction processing - some processors allow parts of instructions to be processed without waiting to complete the whole instruction cycle
  • GPUs - contain lots of seperate processors that can render parts of an image at the same time through pipelining
29
Q

How does pipelining improve CPU performanace

A
  • Reduces CPU idle time
  • While one instruction is being executed, another can be decoded and another fetched
  • This means instructions are exeuted at a faster rate
30
Q

What two forms is pipelining broken down into

A
  • Instruction pipelining - separating out the instruction into fetching, decoding, and executing
  • Arithmetic pipelining - breaking down the arithmetic operations and overlapping them as they are performed
31
Q

What are the potential hazards of pipelining

A
  • Two instructions could be trying to use address bus and data bus at the same time
  • An instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
32
Q

What is Von Neuman Architecture

A

Architecture in which there is a single shared memory and 1 set of buses meaning there is a shared data bus for both data and instructions

33
Q

Describe some of the features of Von Neumann Architecture

A
  • Single control unit
  • One instruction at a time
  • Uses fetch execute cycle
  • Shared memory for data and instruction
  • Single set of shared buses
34
Q

What is Harvard Architecture

A

Architecture in which there are two separate memories and data buses for data and instructions, this is more commonly used with embedded processors

35
Q

What is Contemporary Processing

A
  • A combination of Harvard and Von Neumann architecture
  • Von Neumann is used when working with data and instructions in main memory, but uses Harvard architecture to divide the cache into instruction cache and data cache
  • Makes use of cache, core and pileing
36
Q

What are the advantages and disadvantages of Von Neuman Architecture and Harvard Architecture

A

Von Neumann Architecture -

  • Advantages - Cheaper to develop as the control unit is easier to design. Programs can be optimised in size
  • Disadvantages - The CPU is much faster than the data bus, meaning it often sits idle. Some programs can overwrite another in memory, causing it to crash

Harvard Architecture

  • Advantages - Quicker execution as data and instructions can be fetched in parallel. Memories can be different sizes, which can make more efficient use of space
  • Disadvantages - Limited flexibility as there is only a certain amount of data that can be used for data and certain amount for instructions

Computer Science Paper 1 (16 decks)

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