SRAM, DRAM, ROM Flashcards
What does SRAM stand for?
Static Random Access Memory
What happens to the stored value in an SRAM when we turn off the power?
SRAM is volatile so it is lost
Why do we use SRAM cells instead of D-latches for memory?
They use only 6 transistors (D-latch uses 8) so are smaller and we can create arrays of greater density and therfore greater storage capacity.
Draw an SRAM cell
What are WL and BL in an SRAM cell
Word Line
Bit Line
What is a bus?
A collection of wires carrying signals of same type between subsystems. May be parallel or serial
Describe the Write operation for an SRAM cell
To store a hi in the cell, the bit line (BL) is taken hi, while BL is taken lo (by driver circuitry (not shown)) and then WL is taken hi to allow the bit to be written to the cell, before going lo again to isolate the cell and the bit stored.
Describe how to read from an SRAM cell
When a bit is read from the SRAM cell WL is taken hi to access the SRAM cell and the inverters in the cell drive BL and BL with the bit stored. The transistors in the SRAM cell will be as small as practically possible (to keep the area of the SRAM cell small) and have a weak drive strength to be able to drive the high capacitive load presented by BL and BL . A differential amplifier is used to sense a small differential voltage change between BL and BL resulting from the weak inverters driving their stored values onto a large load capacitance. The sense amplifier (incorporating the differential amplifier, not shown) amplifies this difference and produces a logic level representing the bit stored.
What are the input buses/ signals to a generic SRAM array?
Address bus in k bits
R/W in
Data bus in/out n bits
What is the purpose of the row decoder?
It is the circuit that selects the correct WL given the k-bit address.
Why might we need a column decoder?
When the aspect ratio of the memory gets too large it is not implementable.
We store multiple columns of cells and select them with an address which (using a row and a column decoder) maps to the correct WL
What does DRAM stand for?
Dynamic Random Access Memory
What happens to the contents of DRAM when power is switched off?
They are lost
Describe and draw a DRAM cell
1 capacitor and an NMOS transistor
Describe the write operation of a DRAM cell
- Set BL hi/lo depending on bit to be stored
- Set WL hi to turn transistor on
- Value is stored and capacitor charges/discharges
- Set WL lo to turn transistor off
- The value is stored as the voltage across capacitor
Describe ROM and its inputs/outputs
ROM is an array of memory elements either storing a high or a low.
The elements are addressed by an n bit input address bus
Each location has M bits of data
These appear on the M bit output data bus
Describe the architecture of a CMOS ROM
All BL connected to a load PMOS to VDD.
Data stored as an NMOS connecting to ground if 0 and nothing if 1.
One WL selected at a time which activates any of the NMOS if present, pulling BL to 0, otherwise BL is 1.
