Digital circuits Flashcards
What is an inverter or a NOT gate?
This gate outputs the inverse of its input.
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/219/836/a_image_thumb.png?1659460158)
What is significant about two inverters connected with feedback?
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/220/472/q_image_thumb.png?1659522841)
It creates a stable loop which adopts one of two configurations. This saved value is useful in constructing logic circuits.
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/220/472/a_image_thumb.png?1659460158)
What is this?
When does it conduct?
How well does it conduct when the inputs are high/low?
Is it used in pull-up or pull-down networks?
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/220/582/q_image_thumb.png?1659522841)
An NMOS transistor
On when G is high
Poor conduction if A/B high
Good conduction if A/B low
Used in Pull-down networks
What is this?
When does it conduct?
How well does it conduct when the inputs are high/low?
Is it used in pull-up or pull-down networks?
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/220/856/q_image_thumb.png?1659522842)
A PMOS transistor
On when G is low
Good conduction if A/B high
Poor conduction if A/B low
Used in Pull-up networks
How do you make a digital switch that can be opened/closed using a control signal G?
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/220/854/q_image_thumb.png?1659522842)
Use an NMOS and a PMOS to create a Tx (transmission) gate as shown
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/220/854/a_image_thumb.png?1659460159)
Show how to create a D-Latch using Tx gates and inverters
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/057/q_image_thumb.png?1659522842)
As shown
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/057/a_image_thumb.png?1659460160)
Describe the operation of the D-latch:
While G is high
On the high-low falling edge
While G is low
While G is high the D-latch is in transparent mode where the feedback loop is open and the output Q is simply the input D.
On the high-low edge the current Q output is ‘frozen’ and ignores any further D input changes
While G is low the D-latch is in memory mode and outputs the captured value, regardless of input D.
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/252/a_image_thumb.png?1659460160)
Draw the operation table for the D-latch
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/813/a_image_thumb.png?1659460160)
Draw the Master-Slave arrangement of D-latches required to produce a D flip-flop
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/873/q_image_thumb.png?1659522842)
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/873/a_image_thumb.png?1659460161)
Describe the operation of the D flip-flop when
The clock is low
The low-high transition
The clock is high
in terms of the master-slave arrangement
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/904/q_image_thumb.png?1659522843)
When the clock is low the Master is transparent and the Slave retains its memorised output Q
On the low-high transition the Master stores the input D, while the Slave is transparent. This value is passed to the Slave to output.
![](https://s3.amazonaws.com/brainscape-prod/system/cm/141/221/904/a_image_thumb.png?1659460161)