SLR 01 - Structure and Function of the CPU Flashcards

1
Q

What does the CU stand for?

A

The Control Unit

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2
Q

What does the CU do?

A

Co-ordinates all activities
Directs flow of data
Controls the FDE cycle
Sends memory read/write requests
Uses registers and clock
Communicates with all components

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3
Q

What does the PC stand for?

A

Program Counter

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4
Q

What does the PC do?

A

It is holds the address of the next instruction
This is either:
- The next instruction in a sequence
- The address to jump too when branching
Every FDE cycle the contents of the PC copies into the MAR

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5
Q

What does the MAR stand for?

A

The Memory Address Register

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6
Q

What does the MAR do?

A

Holds the address of the memory location from which a data / instruction to be fetched
Sends the address down the address bus to main memory

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7
Q

What does the MDR do?

A

The Memory Data Register

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8
Q

What does the CIR stand for?

A

The Current Instruction Register

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8
Q

What does the MDR do?

A

Temporary storage of data that is to read from or to be written to memory
Sometimes considered the Memory Buffer Register
All data that interacts with Main memory must pass through the MDR

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9
Q

What does the CIR do?

A

Holds the currently executed instruction
MDR contents is copied into the CIR if it is an instruction
Contains the opcode and operand of an instruction

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10
Q

What does ALU stand for?

A

The arithmetic logic unit

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11
Q

What does the ALU do?

A

Executes all Arithmetic and logic operations
Uses general purpose registers to hold results

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12
Q

What does the Accumulator do?

A

It is a general purpose register to hold data or control information
A CPU with more general purpose registers runs faster

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13
Q

What does the Address Bus do?

A

Carries memory addresses from the MAR to Main Memory

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14
Q

What does the Data Bus do?

A

Carries binary that makes up transmitted information between the MDR and Main Memory

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15
Q

What does the Control Bus do?

A

Carries command and control signals to all components

16
Q

What does the Decode Unit do?

A

A unit that is presented with a sequence of bits from Main Memory
Uses a lookup table to translate these into instructions understood by the CPU
These commands are specific to each processor

17
Q

What does the Status Register do?

A

It contains information about the Processor’s State

18
Q

What does the Clock do?

A

It Synchronises components by generating pulses
This is measured in Hertz (Hz)
The higher the clockspeed the faster the CPU functions.

19
Q

What does the Cache do?

A

It is a small area of fast memory
L1 is a part of the CPU chip
L2 and L3 exist between the CPU and RAM

20
Q

What does FDE stand for?

A

Fetch - Decode - Execute

21
Q

What happens in the fetch stage?

A

The PC is checked as it holds the address of the next instruction
This is copied to the MAR
This is sent along the address bus to main memory
It waits to recieve a signal from the control bus
This can be “read” from the control unit
The contents would then be sent along the data bus to the MDR
The recieved data if an instruction is copied into the CIR
The PC increments to contain the next address

22
Q

What happens in the Decode stage?

A

The instruction in the CIR is decoded by the decode unit
This splits it into it’s opcode and operand
If the operation is load, the data fron the operands location is loaded into a register

23
Q

What happens in the Execute Stage?

A

The address is sent down the Address Bus to Main Memory
The control unit releases a signal down the control bus
The contents of the address is sent down the data bus to the MDR
The contents of the MDR is copied into the ACC

24
Q

What happens if a program branches?

A

If the CIR contains the binary string to branch (e.g 0110 - branch always)
It replaces the value of the PC with that of the CIR
Because the address is differen the program jumps around memory

25
Q

What are the 3 Cs of CPU performance?

A

Clock Speed
Cache Size
Number of Cores

26
Q

How does Clock Speed affect CPU performance?

A

It controls the rate at which CPU components function.
When your clock speed is higher more instructions are processed per second.

e.g 3.2GHz is 3.2 Billion Instructions

27
Q

How does Cache Size affect CPU performance?

A

Because the Cache exists on or near the CPU it can store copies of frequently fetched instructions
It is quicker to access than RAM, meaning if you can avoid fetching from RAM you save time

28
Q

How does the Number Of Cores affect CPU performance?

A

A core is a complete copy of a CPU
Each has its own components
CPUs with multiple cores can execute multiple FDE cycles at any given time utilising Multi-Threading
Not all programs are designed with this in mind, meaning it only plays a part in specific circumstances

29
Q

What are the features of Von Neumann architecture?

A

Shared memory space for instructions and data
Instructions and data are stored using the same format
single Control Unit follows a linear FDE cycle
1 Instruction at a time
Registers are used for fast access of data

30
Q

What are the features of Harvard Architecture?

A

Instructions and Data are stored seperately
Each core has its own buses
Reading and writing Data can happen at the same time (Pipelining)
Used by RISC processors

31
Q

What does SIMD stand for and what uses it?

A

Single Instruction Multiple Data
Used most often by specialised Processors (e.g a GPU)

32
Q

What does MIMD stand for and what uses it?

A

Multiple Instruction Multiple Data
Used by CPUs

33
Q

What is Distributed Computing?

A

Multiple computers on a shared network executing a larger task concurrently.

34
Q

What is Pipelining?

A

A process involving fetching, decoding and executing instructions simulatenously

35
Q

Why is Pipelining used?

A

When not used components risk being sat idley while they could be in use?

36
Q

What are the 2 Pipelines?

A

The Instruction Pipeline

The Arithmetic Pipeline

37
Q

What does the Instruction Pipeline do?

A

It reads the next instructions from memory while others are being executed

38
Q

What does the Arithmetic Pipeline do?

A

It divides a problem into seperate parts to be executed simultaneously