Section 5: Computer Organisation and architecture Flashcards
1
Q
control Bus.
- a bus is a set of parallel wires connecting two or more components of a computer.
- Control bus; a bi-directional bus, the purpose of the control bus is to transmit commands timing and specific status information between system components.
- control lines include - memory write = causes data on the data bus to be written into the addressed location, clock = used to synchronize operations.
A
- a bus is a ___ of ____ wires _______ two or more _______ of a ________.
- _____ __; a __-_____ bus, the purpose of the control bus is to transmit ______ _____ and _____ status information between system components.
- control lines include - ____ write = causes ___ on the data bus to be ____ into the ________ location, clock = used to synchronise operations.
2
Q
Data Bus.
- typically consisting of 8, 16, 32 or 64 separate lines provides a bi-directional path for moving data and instruction.
- the width of the data bus is a key factor in determining overall system performance.
A
- typically consisting of 8, __, __ or 64 ______ lines provides a __-______ path for ____ data and ________.
- the ____ of the ___ bus is a _____ factor in ________ overall system ________.
3
Q
Address Bus.
- Memory is divided up internally into units called words, a word is fixed size group of digits, each word in memory has its own specific address.
- when the processor wishes to read a word of data from memory, the width of the address bus determines the maximum possible memory capacity of the system.
- E.g. if the address bus consisted of only 8 lines, the the maximum address it could transmit would be 2^8 = 255.
A
- Memory is ______ up internally into ____ called ____, a word is ____ ___ group of digits, each word in memory has its own _____ _____.
- when the processor wishes to read a word of data from memory, the ____ of the address bus determines the ______ ______ memory capacity of the system.
- E.g. if the address bus consisted of only 8 lines, the the maximum address it could transmit would be 2^8 = 255.
4
Q
Von Neumann Architecture.
- this specifies the basic components of the computer and processor in which a shared bus is used for both data and instruction.
- a program must be resident in the main memory to be executed.
- the instruction and data are both stored in the same place.
A
- this specifies the basic components of the ______ and _______ in which a _____ bus is used for both ____ and _______.
- a ______ must be resident in the ____ memory to be ______.
- the _______ and ____ are both _____ in the _____ place.
5
Q
Harvard Architecture.
- a computer architecture with physically separate memories for instruction and data.
- used extensively with embedded digital processing.
A
- a computer architecture with _______ separate _______ for ______ and ___.
- used ________ with _________ ______ processing.
6
Q
Control Unit.
- used to control and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices.
- it accepts the next instruction, breaks down its processing into several sequential steps, manages its execution and stores the resulting data back in memory or a registers.
A
- used to _____ and ______ the _____ of the CPU, ______ the _____ of _____ between the ____ and other ______.
- it _____ the ____ ______, _____ down its __________ into _____ ________ steps, manages its execution and ______ the _______ data back in _______ or a _____.
7
Q
Arithmetic Logic Unit (ALU).
- this performs arithmetic and logic operations on the data.
- it can perform instructions such; add, subtract, multiply or divide.
- this operation can be done on fixed or floating point numbers.
it can perform shift operations, Boolean logic operation, compare two values and logical gates such as AND, OR, NOT and XOR.
A
- this performs _____ and _____ operations on the ___.
- it can perform instructions such; ____, subtract, _____ or ____.
- this ______ can be done on _____ or _____ ____ ______.
it can ______ _____ operations, ______ logic _______, ______ two ___ and logical _____ such as AND, ___, NOT and ___.
8
Q
The System Clock.
- this generates a series of signals, switching between 0 and 1, billions of times per second.
- this synchronises the CPU operations.
A
- this ______ a _____ of _____, ______ between _ and _, _______ of times per _____.
- this _________ the ____ operations.
9
Q
General Purpose Registers.
- there are typically up to 16 general purpose registers in the CPU.
- all the arithmetic, logical or shift operations take place in registers.
- an ACCUMULATOR is another general purpose register, used when there is just a single register in which to store the result of each calculation.
A
- there are ______ up to __ _____ purpose ______ in the ___.
- all the _______, _____ or ______ operations take place in _____.
- an ACCUMULATOR is another general purpose register, used when there is _____ a ____ register in which to ____ the ____ of each _______.
10
Q
Dedicated Registers: Program Counter.
- hold the address of the next instruction to be executed.
- or it can hold the address to jump to if the current instruction is a branch or jump instruction.
A
- hold the ______ of the _____ ______ to be ______.
- or it can ____ the _______ to _____ to if the current instruction is a _____ or ______ instruction.
11
Q
General Purpose Registers: Current Instruction Register.
- this only holds the current instruction being executed.
A
- this only ____ the ______ ______ being ______.
12
Q
General Purpose Registers: Memory Address Register.
- holds the address of the memory location from which data or instruction is to be fetched or to which data is to be written to.
A
- holds the _______ of the ______ _____ from which ____ or ________ is to be ______ or to which ___ is to be ______ to.
13
Q
General Purpose Registers: Memory Buffer Register.
- used to temporarily store the data read or written to memory.
- it is also sometimes known as the memory data register.
A
- used to _______ _____ the _____ _____ or _____ to ______.
- it is also sometimes known as the _______ _____ register.
14
Q
The Fetch-Execute Cycle: Fetch phase.
- the address of the next instruction is copied from the program counter to the memory address register, the address is sent via the address bus to main memory.
- the instruction held at that address is returned along the data bus to the memory buffer register, simultaneously the content of the program counter is incremented so that it holds the address of the next instruction.
- the content of the memory buffer register is copied to the current instruction register.
A
- the ______ of the next ________ is _____ from the ______ ______ to the ______ _______ ______, the ______ is sent via the ______ bus to ______ ______.
- the ________ held at that _______ is ______ along the ____ ___ to the _____ _____ register, __________ the _______ of the _______ ______ is ________ so that it holds the ________ of the ____ ________.
- the ______ of the _______ _____ ______ is ______ to the ______ _______ register.
15
Q
The Fetch-Execute Cycle: Decode phase.
- the instruction held in the current instruction register is decoded. The instruction is split into opcode and operand and the opcode is used to determine the type of instruction and what hardware to use to execute it.
A
- the _______ held in the ________ ________ ______ is decoded. The instruction is ___ into ______ and ______ and the _____ is used to _______ the _____ of _______ and what ______ to use to _____ it.