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Computer Systems > Revision - exceptions, virtual memory, cache etc > Flashcards

Revision - exceptions, virtual memory, cache etc Flashcards

1
Q

two types of exceptions

A

internal - traps
external - interrupts

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2
Q

what is an exception

A

an event that disrupts the normal program flow

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3
Q

high level exception mechanism

A
  1. save address of current register
  2. transfer control to the OS at a known address
  3. handle the exception
  4. return to program execution
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4
Q

how is the address of the current register saved (exception mechanism)

A

use the EPC (exception program counter)

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5
Q

how is the exception handled (exception mechanism)

A

the exception handler is found
cause is dealt with

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6
Q

how is the program returned to program execution (exception mechanism)

A

restore user program registers
jump back using the EPC
this relies on eret

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7
Q

two approaches to finding the exception handler

A
  1. cause register
  2. vectored interrupt
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8
Q

cause register

A

jump to predefined address
use the cause register to branch to the right handler

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9
Q

vectored interrupt

A

jump directly to the specific handler depending on the exception

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10
Q

how is an exception dealt with (if restartable)

A
  1. determine the action needed
    - inspect the cause register or opcode
  2. take corrective action
  3. use the EPC (exception program counter) to return
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11
Q

how is an exception dealt with (if not restartable)

A
  1. determine the action needed
    - inspect the cause register or defined opcode
  2. terminate the program using the EPC (exception program counter)
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12
Q

what should happen to other interrupts whilst the exception is being dealt with (and how)

A

other interrupts should not occur
interrupts are masked by setting the EXL (exception level) in the status register

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13
Q

4 advantages of dual mode

A
  1. user programs do not have indefinite control
  2. ensures programs do not have access to resources which they do not have permission for
  3. ensures programs do not interfere with each other
  4. control is transferred to OS when user programs perform dangerous tasks
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14
Q

why are system resources protected

A

to provide safe and orderly access to resources (such as hardware and memory)

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15
Q

what is kernel mode

A

a mode where the OS takes control
it can only be accessed through exceptions
(the kernel is the nucleus of the OS)

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16
Q

differences between kernel and user mode

A

some instructions (such as accessing I/O devices and handling TLB misses) are only accessible in kernel mode

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17
Q

how is the current mode identified

A

a bit in special status register

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18
Q

how do you set the mode back to the previous mode

A

use eret

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19
Q

problems that CPU time sharing solves

A
  • I/O takes too long - leaves the processor idle
  • user programs can crash or use all of the CPU
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20
Q

How does CPU time sharing work

A

switch from one process to another when it performs I/O or when time allocation expires

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21
Q

what is the kernel

A

the core of the CPU that controls software and hardware resources

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22
Q

three active states

A

ready
running
blocked

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23
Q

five steps of process managing

A
  1. exception occurs
  2. process calls OS
  3. process info saved in PCB
  4. new process runs
  5. process states updated

(1. process calls the OS when interrupt / trap occurs
2. OS dispatcher performs a context switch
3. process info is saved in the Process Control Block (PCB)
4. Dispatcher chooses new process to run
5. process states are updated)

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24
Q

Two inactive states

A

suspended ready
suspended block

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25
Q

how does suspending and resuming processes occur

A

processes are moved from memory to disk.
the PCB (process control block) of inactive processes are kept in the OS
inactive processes may be resumed by returning data from disk to memory

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26
Q

what are 4 things contained in the PCB (process control block)

A

process id
process state
process priority
process permission

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27
Q

what is temporal locality

A

the tendency to reuse recently accessed data items

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28
Q

what is spatial locality

A

the tendency to reference data items that are close to other recently accesses items

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29
Q

how do memory hierarchies take advantage of temporal locality

A

by keeping more recently assessed data items closer to the processor

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30
Q

how do memory hierarchies take advantage of spatial locality

A

by moving blocks consisting of multiple continuous words in memory to upper levels of the hierarchy

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31
Q

how can the miss rate be lowered

A

by making larger blocks (which exploit spatial locality

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32
Q

principle of locality

A

a program accesses a relatively small portion of its addresses at any instant of time

33
Q

block / line

A

minimum unit of information that can be present in the cache

34
Q

hit rate

A

fraction of memory accesses in a particular level of memory hierarchy that are a hit

35
Q

miss rate

A

fraction of memory accesses in a particular level of memory hierarchy that are a miss

36
Q

miss rate

A

fraction of memory accesses in a particular level of memory hierarchy that are a missm

37
Q

miss penalty

A

time used to fetch a block from lower hierarchy. this time includes the access of the block , copying and writing it to a new location

38
Q

memory hierarchy (from least to greatest)

A

disk / ssd, main memory, cache, registers

39
Q

fully associative cache

A

a block can be placed anywhere in the cache

40
Q

fully associative cache replacement techniques

A

LRU - least recently used
FIFO - first in, first out

41
Q

direct mapped cache

A

each memory location is mapped to exactly one location in the cache

42
Q

valid bit

A

field in a table of memory that indicates whether the associated block in hierarchy contains valid data

43
Q

tag

A

field in a table of memory that contains the info required to identify the block in hierarchy that corresponds to the main memory block that it holds

44
Q

write to cache (hit - write through)

A

write to both cache and memory

(slow but memory and cache are always synchronised)

45
Q

write to cache (hit - write back)

A

write to cache only

memory is replaced when the dirty cache block is replaced

46
Q

when is the dirty bit set

A

if a block has been written to

47
Q

write to cache (write allocate - miss)

A

bring the block into the cache and modify in cache only

48
Q

write to cache (write - no allocate - miss)

A

modify block in the memory only

49
Q

two issues that virtual memory addresses

A

capacity
safety

50
Q

physical address space

A

main memory

51
Q

name for cache line or block in virtual memory (virtual memory)

A

page or virtual page

52
Q

name for cache line or block in virtual memory (physical memory)

A

page frame or physical page

53
Q

when does a page fault occur

A

when the valid address is not in memory

54
Q

what are the page table permission bits for

A

control whether a process can
- access a page
- modification (read + write / read only / execute only)
- enables memory protection

55
Q

what can change page tables

A

operating system

56
Q

where is the page table located

A

in the system portion of the main memory

57
Q

what is used as a cache for VM

A

physical memory is used as a cache for virtual memory

58
Q

what problem does TLB (translation look-aside buffer)

A

as page tables are stored in the main memory, every memory access requires one access to obtain the physical address and second one to get the data

hence large latency

59
Q

permission bits of TLB

A

– V (valid) bit indicates a valid entry
– D (dirty) bit indicates whether page has been modified

60
Q

what is the TLB

A

a small, fully-associative cache of page table entries

61
Q

how is the TLB accessed

A

– Accessed with Virtual Page Number (VPN)

62
Q

how is the physical address formed by the TLB

A

– Each entry stores the translation (PPN) for a given VPN
– Physical address formed from PPN and Page Offset

63
Q

What is accessed on a TLB miss

A

– Page table accessed on a TLB miss

64
Q

three advantages of having a ISA

A
  • hides hardware details from the programmer
  • enables multiple microarchitectures of the same ISA
  • defines the set of allowed instructions
65
Q

what happens after a cache miss

A

a cache block containing the requested word is copied from memory to cache (hence both the cache and memory have the block)

66
Q

name three things involved in MIPS processor exception handling mechanism

A

vectored interrupt
interrupt mask
cause register

67
Q

name two features of twos complement representation

A

add / subtract operations do not depend on the sign of the operands
sign extension is trivial to perform (right shift - logical or arithmetic)

68
Q

the operating system protects the following systems resources

A

the processors TLB

69
Q

what limits performance of a mulitcycle processor

A

number of cycles needed to complete an instruction
clock frequency of the processor
propagation delay incurred in each cycle

70
Q

name four things that will trigger an MIPS exception

A

TLB miss
disk I/O completion
syscall instruction
user clicking a mouse

71
Q

what is required to build a ripple adder carry

A

requires and, or and not

or

nand

72
Q

what is required to be maintained in a page table

A

bit indicating if
1. the page has been recently accessed
2. the page had been modified after it was loaded to memory
3. the page is resident in memory

73
Q

name three triggers for context switching

A

multi-tasking
interrupt handling
user and kernel mode switching

74
Q

what is context switching

A

storing the context or state of a process so that it can be reloaded when required and execution can be resumed from the same point as earlier

75
Q

4gb

A

2^32

76
Q

1KB

A

2^10

77
Q

2gb

A

2^31

78
Q

1gb

A

2^30

Computer Systems (3 decks)

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