Revision - exceptions, virtual memory, cache etc Flashcards
two types of exceptions
internal - traps
external - interrupts
what is an exception
an event that disrupts the normal program flow
high level exception mechanism
- save address of current register
- transfer control to the OS at a known address
- handle the exception
- return to program execution
how is the address of the current register saved (exception mechanism)
use the EPC (exception program counter)
how is the exception handled (exception mechanism)
the exception handler is found
cause is dealt with
how is the program returned to program execution (exception mechanism)
restore user program registers
jump back using the EPC
this relies on eret
two approaches to finding the exception handler
- cause register
- vectored interrupt
cause register
jump to predefined address
use the cause register to branch to the right handler
vectored interrupt
jump directly to the specific handler depending on the exception
how is an exception dealt with (if restartable)
- determine the action needed
- inspect the cause register or opcode - take corrective action
- use the EPC (exception program counter) to return
how is an exception dealt with (if not restartable)
- determine the action needed
- inspect the cause register or defined opcode - terminate the program using the EPC (exception program counter)
what should happen to other interrupts whilst the exception is being dealt with (and how)
other interrupts should not occur
interrupts are masked by setting the EXL (exception level) in the status register
4 advantages of dual mode
- user programs do not have indefinite control
- ensures programs do not have access to resources which they do not have permission for
- ensures programs do not interfere with each other
- control is transferred to OS when user programs perform dangerous tasks
why are system resources protected
to provide safe and orderly access to resources (such as hardware and memory)
what is kernel mode
a mode where the OS takes control
it can only be accessed through exceptions
(the kernel is the nucleus of the OS)
differences between kernel and user mode
some instructions (such as accessing I/O devices and handling TLB misses) are only accessible in kernel mode
how is the current mode identified
a bit in special status register
how do you set the mode back to the previous mode
use eret
problems that CPU time sharing solves
- I/O takes too long - leaves the processor idle
- user programs can crash or use all of the CPU
How does CPU time sharing work
switch from one process to another when it performs I/O or when time allocation expires
what is the kernel
the core of the CPU that controls software and hardware resources
three active states
ready
running
blocked
five steps of process managing
- exception occurs
- process calls OS
- process info saved in PCB
- new process runs
- process states updated
(1. process calls the OS when interrupt / trap occurs
2. OS dispatcher performs a context switch
3. process info is saved in the Process Control Block (PCB)
4. Dispatcher chooses new process to run
5. process states are updated)
Two inactive states
suspended ready
suspended block
how does suspending and resuming processes occur
processes are moved from memory to disk.
the PCB (process control block) of inactive processes are kept in the OS
inactive processes may be resumed by returning data from disk to memory
what are 4 things contained in the PCB (process control block)
process id
process state
process priority
process permission
what is temporal locality
the tendency to reuse recently accessed data items
what is spatial locality
the tendency to reference data items that are close to other recently accesses items
how do memory hierarchies take advantage of temporal locality
by keeping more recently assessed data items closer to the processor
how do memory hierarchies take advantage of spatial locality
by moving blocks consisting of multiple continuous words in memory to upper levels of the hierarchy
how can the miss rate be lowered
by making larger blocks (which exploit spatial locality
principle of locality
a program accesses a relatively small portion of its addresses at any instant of time
block / line
minimum unit of information that can be present in the cache
hit rate
fraction of memory accesses in a particular level of memory hierarchy that are a hit
miss rate
fraction of memory accesses in a particular level of memory hierarchy that are a miss
miss rate
fraction of memory accesses in a particular level of memory hierarchy that are a missm
miss penalty
time used to fetch a block from lower hierarchy. this time includes the access of the block , copying and writing it to a new location
memory hierarchy (from least to greatest)
disk / ssd, main memory, cache, registers
fully associative cache
a block can be placed anywhere in the cache
fully associative cache replacement techniques
LRU - least recently used
FIFO - first in, first out
direct mapped cache
each memory location is mapped to exactly one location in the cache
valid bit
field in a table of memory that indicates whether the associated block in hierarchy contains valid data
tag
field in a table of memory that contains the info required to identify the block in hierarchy that corresponds to the main memory block that it holds
write to cache (hit - write through)
write to both cache and memory
(slow but memory and cache are always synchronised)
write to cache (hit - write back)
write to cache only
memory is replaced when the dirty cache block is replaced
when is the dirty bit set
if a block has been written to
write to cache (write allocate - miss)
bring the block into the cache and modify in cache only
write to cache (write - no allocate - miss)
modify block in the memory only
two issues that virtual memory addresses
capacity
safety
physical address space
main memory
name for cache line or block in virtual memory (virtual memory)
page or virtual page
name for cache line or block in virtual memory (physical memory)
page frame or physical page
when does a page fault occur
when the valid address is not in memory
what are the page table permission bits for
control whether a process can
- access a page
- modification (read + write / read only / execute only)
- enables memory protection
what can change page tables
operating system
where is the page table located
in the system portion of the main memory
what is used as a cache for VM
physical memory is used as a cache for virtual memory
what problem does TLB (translation look-aside buffer)
as page tables are stored in the main memory, every memory access requires one access to obtain the physical address and second one to get the data
hence large latency
permission bits of TLB
– V (valid) bit indicates a valid entry
– D (dirty) bit indicates whether page has been modified
what is the TLB
a small, fully-associative cache of page table entries
how is the TLB accessed
– Accessed with Virtual Page Number (VPN)
how is the physical address formed by the TLB
– Each entry stores the translation (PPN) for a given VPN
– Physical address formed from PPN and Page Offset
What is accessed on a TLB miss
– Page table accessed on a TLB miss
three advantages of having a ISA
- hides hardware details from the programmer
- enables multiple microarchitectures of the same ISA
- defines the set of allowed instructions
what happens after a cache miss
a cache block containing the requested word is copied from memory to cache (hence both the cache and memory have the block)
name three things involved in MIPS processor exception handling mechanism
vectored interrupt
interrupt mask
cause register
name two features of twos complement representation
add / subtract operations do not depend on the sign of the operands
sign extension is trivial to perform (right shift - logical or arithmetic)
the operating system protects the following systems resources
the processors TLB
what limits performance of a mulitcycle processor
number of cycles needed to complete an instruction
clock frequency of the processor
propagation delay incurred in each cycle
name four things that will trigger an MIPS exception
TLB miss
disk I/O completion
syscall instruction
user clicking a mouse
what is required to build a ripple adder carry
requires and, or and not
or
nand
what is required to be maintained in a page table
bit indicating if
1. the page has been recently accessed
2. the page had been modified after it was loaded to memory
3. the page is resident in memory
name three triggers for context switching
multi-tasking
interrupt handling
user and kernel mode switching
what is context switching
storing the context or state of a process so that it can be reloaded when required and execution can be resumed from the same point as earlier
4gb
2^32
1KB
2^10
2gb
2^31
1gb
2^30
