Exam questions Flashcards
compared to CISC processors, what two features of RISC processors have that can be directly attributed to Moores Law
RISC benefits by
1. having many registers
2. regular ISA
how does a microarchitecture relate to an ISA and explain why it is useful to separate the two
a microarchitecture is an instance of the ISA
many microarchitectures can exist for a given ISA, giving a range of products (can have different price, power etc) and still be binary compatible
state an interesting feature of the exponent
it is bias - avoiding the need for negative numbers and simplifies comparisons
state an interesting feature of the mantissa
it is normalised - simplifies comparisons and allows for a more compact representation
one pro and con about 2s complement
+ simplifies arithmetic circuits, single 0
- range is asymmetric
how does a computer know that a given word is a floating point value, integer of ASCII character
it does not
the instructions tell it what to do with a given word
what is functional completeness
a set of gates sufficient to implement any logical boolean function
name the memory hierarchy from smallest to largest
registers, cache, memory, disk
how is register to cache memory managed
software - compiler
there are very few registers, so explicit management is needed.
need global knowledge to manage scarce register resources
no time for decision making
how is to cache to main memory managed
hardware
cache is not visible to the software
hardware manages them, filling and spilling data from memory
how is memory to disk managed
software -
operating system manages page movement between disk and memory
OS manages virtual memory page swapping
note that file accesses could also be stated to come from the OS (since is manages disk mappings) or the user (who may give the command to open or save a file,
disk is slow therefore software is good enough
what two problems does virtual memory address
limited capacity of physical memory
- multiple programs sharing limited physical memory (solved by OS managed paging between memory and disk(TLB))
memory safety
solution is protection bits in OS and TLB that are checked on every memory access
which is more expensive - cache miss or TLB miss
TLB miss because it involves at least one memory access (same as a cache miss) but also requires a context switch to the kernel to access the page table
list the sequence of events associated with the execution of a lw instruction from the perspective of the memory system
- search the TLB
1.2. on a miss search the page table
1.2.3. on a miss transfer block from disk to memory and update the page table - update the TLB with a V to P translation
- search the cache
3.1. on a miss access the memory and update the cache - return the requested word from the cache to the processor
what is the TLB
translation lookaside buffer
a address translation table contained in the memory management unit of the CPU
it is small and fast
it is a table of triplets in the form [SB, P, F]
SB - status bits (residence, access, modification - RAM)
P - virtual memory page number
F - physical memory frame buffer
why do modern computers have a memory hierarchy rather than a single main memory
the hierarchy achieves a better average case time
what information is stored on a stack
return addresses, passing parameters, saving registers that need to be preserved, keeping local variables
what is a microarchitecture
An instance of the ISA
many microarchitectures can exist for a given ISA, enabling a range of products with different price / performance / power while being binary compatible
explain how the performance of multiprocessor can be improved
performance is a function of cycle count and cycle time
decreasing average cycles reduces the cycle count - this is a win if not accompanied by a proportional increase in cycle time
increasing average cycles can be useful to reduce the number of gates per stages hence reducing the propagation delay and hence cycle time
reduction in cycle time must offset increase in average cycle count
state the action taken by the operating system in response to a page fault
bring in a page from disk and install it in memory
update page table
update TLB
state the action taken by the operating system in response to a I/O stall
context switch to another process
state the action taken by the operating system in response to a load accessing unsafe address
kill the process
why when an interrupt is being serviced, other interrupts should not be visible to the processor
because the EPC and cause registers would be overwritten
what is the purpose of dual mode architecture
to protect critical system resources
resource mangement
scheduling
what trigger switches between the two modes of dual mode architecture
into the kernel - exception
back to user mode - eret instruction / special instruction
why is dual mode used in MIPS
so that user programs cannot access resources or memory allocated to other processes
list the four steps in the MIPS exception handling mechanism
- save the address of the current instruction into the EPC
- transfer control to the OS at a known address
- handle the exception
- return to the user program execution (restore user registers and jump to EPC via eret)
state and explain the three steps needed to compute the target jump address (for beq)
- left shift by two - word align, this increases the addressing range of the offset
- sign extend by 16 bits - needed to form a 32 bit value for address calculation
- add the shifted sign extended value to PC+4 - compute the final address with respect to PC +4
two points on overflow detection
if number with opposite signs are added - NO Overflow is possible
if numbers with identical signs are subtracted - no overflow is possible
how does locality exist in programs
instructions are reused (loops, functions etc)
the program only works on a limited set of data (arrays, temporary variables, objects etc)
what unit requires a sequential circuit for its implementation
S-R latch
name one invalid memory region
register file
name one thing that is not a sequential cicuit
ALU
Name four things that impact processor performance
cycle time
ISA
cycles per instruction
number of instructions
in a processor with caches, an index is used to
location the data in a direct mapped cache
name two statements about the usage of the stack
local variables are automatically allocated there
a function call automatically results in allocation of some stack space
tag, offset and index size of 6 bit address
2 bits
name two mandatory features of a processor
control
data path
The MIPS ISA provides several features that facilitate function calls. Name any two such features and explain why they are beneficial.
JAL instruction, $ra register, registers for passing parameters and return values ($a and $v registers), and support for the stack. In general, stack is the only essential feature. All others are only useful from a performance perspective.
Explain how a stack is used in implementing function calls. What information is stored on a stack?
.
Keeping track of return addresses, passing parameters, saving registers that need to be preserved, keeping local variables.
Name one potential drawback of using a stack as compared to registers for passing function arguments.
Stack-based approach involves more instructions (to maintain stack pointer and for pushes/pops), which reduces performance.
You are designing a new computer and have to choose between either stack- or register-based passing of function arguments and return values. Would you go with a stack or register-based approach? Explain your choice.
Stack, since it’s not limited in the number of arguments and return values.
