Revision day two - logic design, single cycle, multi cycle, MIPS and C Flashcards
Data path
performs the data operations as commanded by the program instructions
control
controls the data path, memory and I/O according to program instructions
disadvantages of single cycle
speed - the cycle time is the Time for the most complex instruction but the average instruction needs less time
cost - functional units cannot be resused within one instructions execution
execution time
instruction count x number of cycles per instruction x cycle time
fetch step
instruction is fetched from memory
increment pc to the next instruction (pc +4)
instruction decode
retrieve the appropriate values from register files
decode the instruction
create control signals that will accompany the execution
calculate the target address - sign extend the immediate, shift left by 2 (word align) and add to (pc +4)
R-format instruction
- perform arithmetic and store output in ALUOut
- write result to correct register
Store instruction
- calculate address - 16 bit offset (sign extended) + first register source operand
- write to memory
Branch instructions
- compare operands using ALU subtraction
if 0 - address target is changed to one calculated in step two
else pc register will remain at PC+4
RISC
reduced instruction set computer
CISC
complex instruction set computer
instruction set architecture
the language of the computer
features of CISC
very few registers
very little memory
features of RISC
more memory + faster clock frequency
fixed length and fixed format instructions (for easy, fast decoding)
big endian
the msbyte of the data is placed at the location with the lowest address
little endian
the least significant byte of the data is placed at the byte with the lowest address
how can a word be stored in memory
- unaligned - placed anywhere
- aligned - at an address which is a multiple of the word size
memory regions and management in c
heap - dynamically allocated memory (managed by the programmer)
stack - for function / method calls (managed by compiler)
static - for data that lives during the whole lifetime of the program (initialised when the process starts
extern
extends the scope before the definition and to other files
static
lets it hide from other files
what does xor instruction do
inverts the bits
in a processor with caches, an index is used to
locate the data in a direct mapped cache
data representation affects what two things
circuit complexity
circuit speed
name one thing that will not trigger a processor exception
cache miss
combinational logic
logical system whose blocks do NOT contain memory
computes some output given some input
sequential logic
logical system whose blocks contain memory
hence the output depends on the input and current values in the memory
three ways all logical circuits can be built
and, or, not
nand
nor
decoder
a logic block that has n-bits input and 2^n bits output where each output is asserted for each input combination
multiplexer (MUX)
output is one of the inputs selected by a controller
what does a multiplexer consist of
- detector that generates n different input values
- array of n AND gates
- one OR gate (that combines the output of the AND gates)
32-bit adder
a circuit made by connecting 32 adders
propagation delay
time between input signal change and output signal change at the other end
three things that the propagation delay depends on
- technology
- delay through each gate
- number of gates driven by gates output
asynchronous
state of circuit changes whenever input changes
(there is no clock)
synchrouous
state can only change at times synchronised to an external signal (or clock)
edge triggered clock
clock scheme in which all changes occur on the clock edge
D flip flop
a memory element for which an output is equal to the value of the stored state inside the element
for which the internal state is changed only on the clocks edge
D latch
A memory element for which an output is equal to the value of the stored state inside the element
for which the internal state changes whenever the appropriate input changes and clock is asserted
setup time
the minimum time that the input to the memory device must be valid before the clock edge
hold time
a minimum time during which the input must be valid after a clock edge
Two details of the FSM
synchronised, every change happens in a clock cycle
sequential logic can be described via a FSM
glitch
when different inputs have different delays
Moores law
the number of transistors doubles every 18 - 24 months. at the same time the cost of the transistor reduces
compiler
a program that translates a high level language (C, java) into aa sequence of assembly language statements
assembly language
a symbolic representation of machine instructions
operating system
a supervising program that manages all programs in a computer such as
1. basic I/O interaction
2. allocation and memory
3. protection of sharing the computer
load instruction
- calculate address - 16 bit offset (sign extended) + first register source operand
- read from memory
- store in destination register
