Processor performsnce Flashcards
Words
Memory is divided into equal units called words
Word length - 8, 16, 32, 64 bits
Each word has seperate memory address
What determines max possible memory addresses of the system
Width of address bus
8 bit address bus - 2^8 mem addresses
What direction does data pass thru data bus
both directions
width of data bus defined by
number of lines it contains
data bus same width as comp word
Data can be transferred to and from memory in single operation
What determines format of machine code instruction
architecture of comp; inc: word size, width of address bus
clock speed
and ghz to ticks per sec
faster clock speed - faster a computer can carry out FDE cycle
4 ghz - clock ticks 4bn times a second
System clock
Series of ON/OFF signals used to sync operations of cpu components
actions usually carried out on rising edge of clock
Actions take fixed num of cycles to complete
dual core comp design?
2 processors linked together in same integrated circuit
why can software not take full avantage of nom of cores
some programs not designed to use multi cores
Parallel processing
and why it may not always be possible
Several cores working at same time
each core works concurrently on 1 task
not always possible as insturctions are processed sequentially
where is L1 and L2 cahce
on the cpu
what is l1 cache split into
instruction cache and data cache so instructions and data can be fetched simultaneously
Pipelining
technique used to imporve performance by verlapping stages or breaking don stages in an arithemtic function
pipelining how it works
instruc enter pipeline, as soon as 1 stage of instruc done, another instruc enter pipeline
3rd instruc then enters before either of instrucs completed
