Processor components Flashcards
Whats a bus
a connector that transfers signals between internal components.
typical num of lines in a bus
8, 16, 32, 64 lines
link b/w control bus + processor, I/O, memory
sends control signals to all of them + receives control signals from them
link b/w data bus + processor, I/O, memory
sends and receives data from all three
link b/w address bus + processor, I/O, memory
adress sent from processor to it ONLY
sneds addresses to MEMORY only
sends and receives addresses to/from I/O
5 control signals
memory read/write
bus request/grant
clock
memory read
data from addressed location in ram placed on data bus
memory write
data on data bus written into addressed location in ram
bus request
indicates device requesting use of data bus
bus grant
indicates CPU has granted access to data bus
clock
synchronises operations
operations of ALU
performs arithmetic, logical and shift operations on data
accumulator
general purpose register where results from ALU stored
the dedicated registers in the CPU
Program counter - holds mem address of next instruc to be executed
CIR - holds current instruction which is split into operand + opcode
MAR - hold address in mem where processor is required to fetch or store data to/from
MDR - temp holds data moving between processor and main mem
ACC
opcode
specifies insturction to be carried out
operand
holds either:
address of data to be used, which is then copied to MAR
actual data to be operated on which is passed to MDR
FDE cycle
PC holds address of next instruction to be executed
MAR copies memory address from PC
Data of memory address in MAR copied to MDR, if additional data needed, MDR fetches it. Simultaneuously, PC is incremented.
Contents of MDR copied to CIR
CIR decodes instruction - break down to operand + opcode. If additional data needed, fetched from RAM, passed to ACC.
Instruction executed
