Part 1: Topic 4 - Timing Analysis Flashcards

1
Q

clock period must be greater than…

A

…the delay through the combinational logic blocks

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2
Q

Combinational Logic Timing Parameters - what are the definitions of the parameters shown here?

A

tcd is known as the contamination delay - this is the time it takes for the output to start changing after the input has been changed.

tpd is known as the propagation delay - this is the time it takes for the output to be stable after ‘glitching’

glitching - the changes before

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3
Q

Setup error condition equation

A

Setup error condition determines the minimum clock period which can be used.

The equation can be rearranged for Tc to give the minimum period clock peroid to avoid setup errors.

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4
Q

What is the critical path?

A

The timing path with the longest delay is known as the critical path.

The delay of the critical path is used in the setup condition to determine the minimum clock period and hence the maximum clock frequency.

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5
Q

What does the timing path with the shortest delay tell us?

A

If the path causes glitching by changing values before others have taken affect, this will be noticed.

The shortest delau can be used to determine the critical contamination delay and hence will be used to determine if hold conditions will occur.

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6
Q

What is the equation for the rising propagation delay of a CMOS inverter?

A

Rn and Rp - Rn is the effective resistance of the n-MOSFET channel and Rp is the effective resistance of the p-MOSFET channel

Cn & Cp - respective input gate capacitance for n-MOSFET and p-MOSFE

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7
Q

What is the equation for the logic gate propagation delay?

A
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8
Q

What is Dennard Scaling?

A

“Basic operation of MOSFET is maintained and performance is increased if all dimensions, voltages and dopant concentrations are scaled by factor, S.”

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9
Q

Effect of temperature on CMOS inverter?

A
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10
Q

Corner Analysis

A

FF (“fast”, 0°C temperature, fast process): worst case for hold errors

SF (“fast” 0°C temperature, slow process): demonstrates operation over full temperature range

SS (“slow” 70°C temperature, slow process): worst case for setup errors

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11
Q

Does current flow from the drain to the source?

What about electron flow?

A

Conventional current flows from the drain to the source.

Since electron flow is in the opposite direction of current flow, electrons move from the source to the drain.

Which according to the nomenclature, makes sense.

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