Exam Prep Deck Flashcards
What factors limit the increased throughput that can be obtained using pipelining in complex designs such as a microprocessor data path?
Diminishing returns with each pipeline stage added due to the setup and propagation times of the flip- flop. Also, complex circuits such as the microprocessor data path have dependencies between the pipeline stages (data and control hazards) which require additional logic and delays to overcome and hence do not achieve the expected speed up.
Question iii)
The critical path length is now (3 x RAM delay) + (3 x mux delay) = (3 x 500ps) + (3 x 50ps) = 1650 ps
The minimum clock period = critical path + setup + clock-to-Q = 1650ps + 50ps + 70ps = 1770 ps
Maximum clock frequency = 1/2870ps = 565MHz
Briefly describe the verification process for digital designs
The desired behaviour of the digital circuit is captured in a HDL (hardware description language_)_ such as SystemVerilog. A set of test inputs or “test vectors” are generated which cover all the expected operating conditions of the circuit. Another HDL code, the test bench, is used to apply the test vectors to the circuit in simulation and the outputs are captured. A software model of the circuit behaviour is also created. The HDL simulation and software model outputs are compared to detect logical errors in the HDL code before synthesis starts. This process reduces the probability that defects will be present in the final product.
Architecture
Price lowest to highest: ASIC -> Microprocessor -> FPGA
Define Setup error
The input to a sequential element such as a flip-flop must be stable a certain time before the clock edge, known as the setup time. A setup error occurs when this condition is not met.
Work out DCO tune as an integer?
- Pick a range(DCORSEL).
- Select the desired frequency within that range (FDCOnom).
Explain the following terms in the context of the digital design process.
(i) Constraints
(ii) Recurring costs
(iii) Non-recurring costs
Constraints: requirements which have been identified for the design, for example, minimum clock frequency, maximum delays, maximum area etc.
Recurring costs: costs which have to be paid each time a chip is manufactured, including fabrication, testing and packaging
Non-recurring costs: costs which must be paid before a chip can be manufactured, including design and tooling costs
Specify the contents of the RAM blocks in a CLB to create a 2:1 multiplexer
Assign I0 and I1 on the 16x1bit RAM to be the 2 bits of D. Assign I2 on the 16x1bit RAM to be S, I3 is a “don’t care”.
A single CLB can represent the mux with the following RAM entry:
(to get the address values just combine all the row elements from left to right.
I0 is 4 zeros followed by 4 1s
I1 is alternating sets of pairs
I2 is simply alternating going down.
I3 is just x’s for all the bits.
(i) Explain how the current state variable is updated using the state table implementation approach in c code.
The new state is simply updated using array indexing where the row index is the event value and the column index is the current state. The updated state is given by the value at this memory location.
state = statetable[event][state];
4:1 multiplexor a behavioural style with case statements
Define what is meant by static timing analysis.
In static timing analysis, the delay of every combinational path between sequential elements is calculated. These are used to assess whether each sequential element meets it’s setup and hold conditions under a set of timing constraints such as clock frequency and jitter.
Write C code to implement the action handler for the actiontable, assuming there is a current state variable currentstate and an event variable event. You can assume the action functions: fcn0() … fcn3() are already defined.
Do q b)
Sketch the block diagram of the circuit in terms of the adder and flip-flop cells.
ii)
What is a precision ADC?
module that can achieve over 16bit precision using software oversampling, up to 1 Mbps sampling rate with differential and single ended inputs.
Describe the concept of corner analysis and how it would be applied to variations of Vdd across a digital integrated circuit.
Corner analysis ensures that a high proportion of the chips fabricated will work across all the process and environmental variations. It involves carrying out static timing analysis at the extreme operating conditions or “corners”.
In the case of power supply variation, gates with a low value of Vdd will run slow and hence be more susceptible to setup errors. Gates with high Vdd will run fast and be more susceptible to hold errors. A corner analysis including Vdd variation could include static timing analysis with (1) low Vdd, slow transistors due to process variation and high temperature to ensure that setup errors do not occur and (2) high Vdd, fast transistors and low temperature to ensure that hold errors do not occur.
When using an input pin on a microcontroller as an analogue input what will the input impedance be?
The pin will be in the high impedance state
Explain how Pulse Width Modulation (PWM) is used to control the speed of the motors and describe how it is implemented in microcontroller hardware.
What are the key words/terms you need to remember
PWM is a method of producing an analogue voltage level from a digital output. A PWM signal consists of a periodic pulse train whose frequency is much higher than the frequency of the device or system that is been driven. The signal amplitude is then adjusted by varying the pulse duration or duty cycle. The output waveform is then lowpass filtered, either by a specific low pass filter or simply by the response time of the system that is been stimulated, to produce the analogue waveform. In a microcontroller this is implemented using a timer/counter and two counter compare registers. The timer/counter is clocked at a certain rate 𝑓𝑐𝑙𝑘 using a divided version of the system clock. One counter compare register is used to set the maximum count and hence the period of the PWM signal i.e. 𝑇 = 𝑀𝑎𝑥𝐶𝑜𝑢𝑛𝑡 / 𝑓𝑐𝑙𝑘 . The other compare register is used to set the duty cycle and hence the output amplitude.
Key words/terms to remember: analogue voltage level, periodic pulse train, duty cycle, low pass filter, timer/counter, counter compare registers, maximum count, output amplitude
Explain what is meant by Dennard scaling in the semiconductor industry.
Define pipelining
Partitioning a circuit or algorithm into multiple stages, separated with sequential elements, in order to increase the clock speed and throughput.
Pipelining involves splitting up the functions performed by the combinational logic into separate functions and inserting sequencing flip-flops or registers into the path. Because the delay of the combinational logic in each pipeline stage has been reduced, the clock frequency can be increased or supply voltage can be reduced to save power.
(iii) What is the maximum throughput of the circuit, i.e. the number of sum outputs generated per second?
The minimum clock period is the sum of 3 adder cell propagation delays and the flip-flop setup and clock-to-Q propagation delays.
Minimum period = (3*300ps)+50ps+65ps = 1015ps.
The maximum clock speed or throughput is, therefore, 1/1315ps = 985MHz
Note that they cheekily put maximum propagation delay of adder cells outside of the table.
16 bit vs 8 bit
The 16-bit processor will be two times faster.
Define: Non-recurring costs
Non-recurring costs are any costs which must be paid before any products can be fabricated including d_esign engineering costs_, prototyping, product–specific equipment required for design, product-specific manufacturing equipment such as photomasks and packaging tools
Define Standard Cell Library
A set of predefined characterized layouts of basic logic functions such as AND, OR, invert, flip-flop, latch, multiplex etc. The cells have fixed height and variable width to allow a circuit layout on a regular grid, speeding up development times.
Write C code to initialise pins 0-3 on PORTC as inputs with pull-ups enabled and 4-7 as outputs set to logic high. Then store the state of pin 3 as a char. You may assume that PORTC, DDRC and PINC are defined
DDRC=0xF0;
PORTC=0xFF;
char state=(1<<3)&PINC;
Show how to build a 4:1 multiplexer with the minimum number of CLBs.
A 4:1 mux can be built from 3 x 2:1 muxs arranged in a tree structure. The minimum number of CLBs is therefore 3.
Explain the advantage that the state table implementation provides in comparison to a nested if statement implementation.
In the state table approach the functionality of the machine is encoded in the state transition and action tables and an identical piece of code is used to implement the state machine regardless of the complexity of the machine. This means that the operation of the machine can easily be changed by simply updating the state table without needing to change the code. If the nested if approach is used then the code must be changed which is harder to keep track of and debug.
ADC Interfacing system
Transducer Interface Design (TID) circuit:Scale and shift transducer output signal range.
Scale: Map the span.
Bias: Shift scale to align with ADC input.
V2max = (V1max*K)+B.
V2min = (V1min*K)+B.
Total Power Consumption of circuit with sequential elements
A microcontroller with a clock frequency of 16MHz is used to create an analogue output using PWM suitable for the reproduction of voice signals recorded with 7 bit resolution.
(i) How many bits does the counter require to provide the required resolution and what should the maximum count value be set to?
The counter would only require 7 bits to provide the required resolution, however the dedicated counters in a typical microcontroller are either 8 or 16 bit, using a 8 bit counter with the maximum count set to 127 would provide the correct resolution.
how do you find the maximum count from 7bit resolution? 27 - 1. So 2n - 1 is the formula.
Explain what is meant by the following terms, relating to the timing of synchronous sequential circuits:
2018 - q2 - a
(i) For the circuit to sample its input correctly, the input must have stabilized at least setup time, tsetup, before the active edge of the clock. (so the input was be stable for set amount of time before active edge)
(ii) For the circuit to sample its input correctly, the input must remain stable for at least the hold time, thold, after the active edge of the clock. (so input must remain stable for hold time after the active edge)
(iii) When the clock’s active edge occurs, the output may start to change after the clock to-Q contamination delay, tccq.
(iv) When the clock’s active edge occurs, the output must definitely settle to the final value within the clock-to-Q propagation delay, tpcq.
Table you need to remember to convert binary to hexadecimal
note that the change from number to letter is from 9 to 10
Explain the meaning of line 3 of the code in Figure 1.1
Defines two bit vectors I and Q each with 8 bits. The logic type is used in SystemVerilog to model signals in digital circuits – it has 4 possible values 0, 1, X (unknown) and Z (high impedance).
The circuit above is to be used in a low power application.
(i) Explain how pipelining can be used to reduce power consumption of the circuit without reducing the clock frequency.
Placing the two combinational functions in different pipeline stages means that the delay in each combinational function can be increased by reducing the supply voltage. In this case, it is the 2nd combinational stage which will limit the performance. The current clock frequency can be maintained if the delay of the 2nd combinational stage is increased to 1.5ns.
Key thing to remember is that delay in each combinational element of the pipelined circuit can be increased by reducing the supply voltage, leading to the same clock frequency but lower power consumption.
bit width of ADC module
32-bit
Pointers
A pointer is a variable whose value is the address of another variable, i.e., direct address of the memory location.
Pointers always begin with an asterisk *
Pointers should be initialised as NULL when the intended address is not known.
Uninitialised pointers can be pointing to a memory address used by the system unintentionally.
Allows NULL checks before accessing a pointer
Do questoin b)
i) Draw the equivalent circuit for calculation of the rise/fall times.
If the code in Figure 1.1 was simulated, sketch a waveform showing the signals clock, reset, enable, direction and I from the start of simulation up to 250 ns. Express the values of I in hexadecimal. Ensure that the times of signal transitions are clear.
CMOS Switching energy:
2018 - 3 - c)
Calculate the reduction in power consumption that can be achieved by pipelining without changing the clock frequency, activity factor or threshold voltage and assuming that a single power supply is used for the whole circuit.
Note that the new tpd is 1.5ns for the pipelined circuit with the same frequency as the original circuit.
Multiplexors an pipelining
The combinational logic of the 32:1 mux must be split into 2, ideally with roughly equal critical paths. As the critical path of the 32:1 has 5 x 2:1 stages, it cannot be split equally so the optimum is to have 8:1 muxs in 1 pipeline stage and 4:1 in the other (the 8:1 and 4:1s are constructed from 2:1 building blocks as previously described)
The clock frequency is increased because the critical path is now through the 8:1 mux which consists of only 3 CLBs.
Microcontroller Question
Maximum clock frequency of multiplexor
Following from the answer to (b), the number of stages in an N:1 multiplexer is log2(N). Since the N=32, the critical path is through log2(32) = 5 CLBs.
The critical path length is (5 x RAM delay) + (5 x mux delay) = (5 x 500ps) + (5 x 50ps) = 2750 ps
The minimum clock period = critical path + setup + clock-to-Q = 2750ps + 50ps + 70ps = 2870 ps
Maximum clock frequency = 1/2870ps = 348MHz
In this case the ram and multiplexor delays are multiplied by 5 and the one time setup time clock-to-Q delay are added.
If you applied pipelining to this circuit, what do you need to remember?
the slowest combinational logic block will dictate the new minimum clock period and hence maximum freq.
In any previous clock period can have 0.5ns removed.
What does adding a 3 stage pipeline do to the maximum clock frequency of this circuit?
a register would be placed after each adder cell
maximum clock frequency would increase 3 fold in this case.
Dennard Scaling
Describe the operation of the shift register, in particular, specifying how the output, R, changes in response to the inputs.
If the reset is high (independent of the clock), R is held at 0.
If select S is high, on each positive clock edge, R takes the value of the input I.
If select is low, on each positive clock edge, R is shifted to the left by 1 bit with a zero inserted into the least significant (right-most) bit.
Remember the curly brackets with two or more terms inside means concatenation. In this case everything up to N-2 is selected and a zero is added to the end. Thus R is getting shifted to the left by 1 bit at a time.
ADC subsystems
Action table
The action table contains the function codes for each possible state and input condition. The correct function is determined by doing a lookup using the event value for the row and the current state for the column index.
An inverter in a standard cell library implemented in a 45 nm CMOS process has the following measured propagation delays at the typical corner, shown in Table 3.1
Explain why the inverter cell has finite propagation delay at zero load capacitance.
Chains of logic operate by each logic gate charging/discharging the gate capacitance of the load logic gates. The gate capacitance of the MOSFET is essential to the device operation, but the source and drain also have a capacitance which is parasitic. The propagation delays at zero load capacitance are due to the charging/discharging of this parasitic capacitance.
Reducing power consumption of digital circuits
For each of the following SystemVerilog code fragments, state whether it represents a realisable digital circuit and explain why.
Example (i) is not a real circuit. In simulation, always_comb blocks are executed when any of the right hand side parameters change, so this code will advance count by 4 each time it executes but continue executing for ever at the same simulation time. On the other hand, (ii) is a correct counter as it uses sequential logic which is only executed on the positive clock edge.
Fragment (iii) is correct and represents 4 AND gates operating in parallel. New values of c will be generated whenever any value of the arrays b or a change.
Dennard Scaling limitations
Both oxide thickness and threshold voltage have reached scaling limits. Scaling oxide thickness further causes leakage current to increase due to tunneling. Scaling threshold voltage causes sub-threshold currents to increase when the MOSFET is off. In both cases, further scaling would cause leakage power to dominate overall power consumption which is already a problem for high performance digital systems.
scaling oxide thicknes -> leakage current b/c of tunneling
scaling threshold voltage -> causes sub-threshold currents
thus further scaling causes leakage power to dominate
Total power consumption of a circuit with sequential elements?
timing constraints: hold time
2018 - q2 - b
Explain the meaning of line 6 of the code in Figure 1.1.
Line 6 “instantiates” or defines a submodule within the tb_shiftreg module. In this case the module name is shiftreg and it is given the label uut. The shiftreg module has 1 parameter which in this instantiation is given the value 4. The Q, I, direction enable, clk, reset signals are connected to the ports of shiftreg in the order that they are defined in the code.
So when you don’t know the order of the values of a module instantiation in a module you just assume the order in which they are defined in the parent module?… i guess just remember to state that the order is that which is defined in the code.
Block diagram of ADC-SAR
Critical Path: Sketch a timing diagram for the critical path, and calculate the maximum clock frequency.
2018 - q2 - c)
Explain the changes to the SystemVerilog code that are required to make the reset synchronous?
The sensitivity list for the always_ff block contains posedge reset, meaning that the block will be active when the reset goes high whatever the state of the clock. Removing posedge reset from the sensitivity list will ensure that the reset only triggers on the positive edge of the clock:
Switch Model Circuit Diagram
2018 - q3 - a
Specifically what does the third line do?
as you can see there is a *() with the pointer address +2 inside.
with the *(address+2) you are saying you want the value two places down from addresses poisition.
C programming: what does this mean?
creates a 2x3 matrix called statetable of type char
