Part 1: Topic 2 - SystemVerilog

Question 1

What do modules represent in SV?

Answer 1

As SystemVerilog is a hardware description language, a module represents a circuit block.

Question 2

What are all signals defined as in SV?

Answer 2

they are defined as type logic

e.g. logic c1;

Question 3

What are binary bitwise operators?

Answer 3

SV bitwise operators are used to perform a bit-by-bit operation on two inputs, producing a single output.

They take each bit individually and perform a boolean algebra operation with the other input

Question 4

What is the table of bitwise operators for SV?

Answer 4

Question 5

What is the 1s complement useful for?

What is its main downfall?

Answer 5

The main benefit of using the 1s complement is that the addition of a positive number and a negative number gives the correct answer (provided the answer is negative…)

The main issue is that there is a dual representation of zero.

Question 6

What is the 2s complement?

Answer 6

Modification of the 1s complement that allows for a unique representation of zero.

By adding 1₂ to the 1s complement of the negative number we remove the value -0(negative zero).

You add 1 to the end and remember to take into account any carryover.

2s complement is only for negative!!

You can now add negative and positive values even if the output is positive.

Question 7

What is the 2s complement of 2?

Answer 7

We can remove the negative sign as we are only looking at the magnitude, the sign bit 1 is in fact still there, just not shown…

So you determine binary value for non-negative value, then invert the bits and add one at the end.

Question 8

What is the value of 6 - 2 using 2s complement negative numbers ?

Answer 8

Remember 2s complement essentially inverts the its so it make sense for it to be 11110.

Note that 6 does not have to be converted to 2s complement, its only the negative values.

Apparently the carry is ignored..

Question 9

What is the value of -2 - 6 using 2s complement negative numbers?

Answer 9

Question 10

What do synthesisers do?

Answer 10

convert the behavioural model into the most suitable structural model for the physical technology

Question 11

Behavioural vs Structural modelling

Answer 11

Structural modelling - structural (instantiating primitive entities, e.g. logic gates gates and flip-flops). It is like connecting and arranging different parts of circuits available to implement a functions you are looking for.

Behavioural - (if then, case statements etc.). Writing algorithm type of code.

Structure - using primitives to get end result

Behavioural - using code to get the result

Question 12

Does a always_comb block need a need begin/end statements if the block only consists of 1 clause?

Answer 12

No it doesn’t.

Question 13

What is a case statement?

Explain how it works with reference to the attached module.

Answer 13

The case statement is a decision instruction that chooses one statement for execution. The statement chosen is one with a value that matches the value of the case statement.

The case statement takes in the value for the variable IN. The 3’b000 refers to a 3 bit binary value, in this case the IN variable. What the respective lines are saying is that if IN is equal to the binary value of that line set the OUT variable to the specified value.

Question 14

What does this line say?

Answer 14

The ‘x’ represents ‘dont’ care’ meaning the respective bit can take any value, in this case 0 and 1.

if a 3 bit binary input of value

Question 15

Write a 4:1 MUX using always_comb

Answer 15

Question 16

Write a 4:1 Mux using a case statement

Answer 16

Question 17

200ps B = 2;

What does this mean?

Answer 17

Means wait for 200ps of simulation time before continuing execution of the block.

Question 18

What is a test bench

Answer 18

A SystemVerilog module which is used to test a synthesisable module in simulation.

Question 19

Property of a Sequential Logic System?

Answer 19

The outputs depend not only on the present inputs but also on all previous inputs over a specific operating time.

Question 20

Function of a storage logic system ?

Answer 20

Storage of information (data is input and stored but nothing is output)

Access of information (data is output without data input)

Question 22

The relationship between combinatorial, sequential and memory systems

Answer 22

• A simple sequential circuit has memory properties.
• A combinational logic circuit can be converted into a sequential system by applying feedback from some of the outputs to form additional internal inputs.
• A memory circuit can be organized as a combinational logic function.

Question 23

What does this flip flop tell us?

Answer 23

The @(…) clause is the sensitivity list. This specifies the conditions under which the always_ff block will execute in simulation.

Thus, , on the positive-going edge of the clock, the signal Q takes on the values of D.

Question 24

What do you have to remember about specifying sequential logic?

Answer 24

The <= operator is used when assigning values during sequential operation, this is known as a non-blocking assignments.

Question 25

What is the main difference between an SR flip flop and D flip flop?

Answer 25

The D in D flop stands for Data.

The main difference is that a D flip takes in one input. For the S and R, however, it has an inverter for the R. Thus, S and R never have the same value, which removes the invalid S=1 and R=1 condition of a SR flip flop.

Question 26

How does a D flip flop store information?

Answer 26

D flips change value depending on the clock.

If D has changed, but the cock is equal to 0, the value of Qn will simply be equal to the previous value. Thus, it has memory.

Question 27

Explain this 4 bit register model.

Answer 27

As you can see from the timing diagrams, the value of Q only changes on the positive edge of the clock cycle.

Also, Q is defined by a non-blocking assignment.

Clearly Q only changes after D has changed…which is why we only see a change after the second clock trigger.

Question 28

What is the @(…) clause?

e.g. always_ff @(…)

Answer 28

The @(…) clause is the sensitivity list. This specifies the conditions under which the module block will execute in simulation.

Usually the module in question is always_ff.

Question 29

What does always_ff represent in SV?

Answer 29

Represents a flip-flop (ff), the process is triggered (executed) on every positive edge of the clock. This replaces always @(posedge clk). This is the only type where non-blocking (<=) assignments should be used, as this mimics the way a flip-flop transfers data.

Of course, you can add a sensitivity list to alter the clk.

Question 30

What do always and intial mean in SV?

Answer 30

always is the main type of process from Verilog, it continues running throughout the simulation, the other is an initial which is ran once at the start of a simulation.

Question 31

In SV what does the for loop represent?

Answer 31

It represents duplicated parallel logic.

In this case a chain of D flip-flops

Question 32

Question in Part 2 of Notes

Answer 32

Question 33

What does ? : represent in SV?

It takes values in between and around the ? and :

e.g. a ? b : c

Answer 33

It is a conditional operator.

The operator returns b if a is true, otherwise c.

Question 34

How many bits does this variable hold?

How many possible values does it have?

logic [4:0] f

Answer 34

5 bit

32 possible values.

Question 35

With SI = 0 and sr = 00100000

What would the value of sr and SO be after one iteration?

Answer 35

the values would be concatenated to form => 000100000

Since the assignment {sr, SO}, sr = 00010000 and SO = 0

So sr was shift to the right by one place.

Question 36

What sort of period does this clock have?

Answer 36

It has a 10ns period.

every 5ns change the clock to the opposite value. It would take two changes to make one period, which is why its a 10ns period.

Question 37

If you have two initials processes in code, do they start in parallel or does the environment go through the processes in order of position in the code?

Answer 37

for initials, SV goes through line by line, thus an inital process stated higher up will occur sooner.

Question 38

In a module, are always statements read in order of position in the code or are do they run in parallel?

Can they run before initial statements?

Answer 38

They run in parallel.

Apparentely they can, however, usually they need a clock edge to run, which is why any values inside the always statement would be unkown until this happens.

Question 39

Why is S_reg still at 0 after the reset change?

Answer 39

From the code it can be seen that reset changes 0 after 10ns, which means that S_reg will no longer be assigned to 0. However, the code inside always_ff is only read on the positive rising edge of the clock and ‘reset’ is not part of the sensitivity list, i.e. a change ‘reset’ isn’t immediately picked up.

The system still has to wait 5ns to reach the rising edge.

We can notice that on the first positive clock edge S_reg is set to 0 because reset is equal to 1. Before that it was ‘unkown’ because it hadn’t been assigned at all yet.

Question 40

Why is this wrong?

Answer 40

4 bits can’t hold 17

Maximum 4 bits can hold is 16.

SV will truncate values that are too large for the bits they are being assigned to.

Question 41

How can this assignment be written in binary form?

Answer 41

Negative binary values need to be written in 2s complement.

Question 42

What is the rule for blocking and non-blocking assignments that you need to remember?

Answer 42

Use blocking assignments for combinational logic and test benches.

Use non-blocking for sequential (edge-triggered) logic (synchronous).

Question 43

What does { } with variables inside mean?

Answer 43

Concantenation

Question 44

What is the value of the first binary term?

Answer 44

first term is equal to 2⁰ = 1,

so either 1 or 0.