Packaging

Question 1

What is a SOC?

Answer 1

System on a chip - a single chip that has all the essential functions such as processing, memory, graphics, sound, etc.

Question 2

Why is packaging necessary?

Answer 2

1. Protect the chip from the environment and from handling
2. Interconnects between the chip and other components
3. Physical support for the chip
4. Heat dissipation

Question 3

What properties are desirable in packaging?

Answer 3

1. Electrical - low parasitic
2. Mechanical - reliable, good mechanical properties
3. Thermal - efficient heat removal
4. Economical - cheap

Question 4

What are the steps in traditional packaging and assembly?

Answer 4

1. Wafer test and sort - the wafer is tested and non-functional die are marked
2. Die separation
3. Die bonding - attachment to package
4. Wire bonding or other method of bond to package connections (electrical connections)
5. Plastic packaging
6. Final packaging and test

Question 5

What is die bonding? How is it accomplished?

Answer 5

Attachment of the bottom of the die to the plastic package. This must have good adhesion in order to provide good mechanical protection and heat dissipation.

Some types of bonding:

• Eutectic Au/Si mixture (high-tech, expensive)
• Epoxy (cheap)
• Polyamide glue

Question 6

What is wafer sorting?

Answer 6

Testing each die and marking the nonfunctional die. This is carried out before die separation so that only known good die proceed to packaging

Question 7

What is the difference between a die and a chip?

Answer 7

A die becomes a chip after it is packaging

Question 8

How is the wafer diced?

Answer 8

Wafer dicing is accomplished by cutting along the ‘scribe lines’, non-functional lines along the wafer.

Usually, a water-cooled circular saw with diamond-tipped teeth is used

Question 9

How does wire bonding work?

What issues are there with wire bonding?

Answer 9

In wire bonding, each good die is attached to a leadframe. The bond pads on the outer edge of the die are attached to the leadframe with wires. After bonding, mechanical tests (die shear/wire pull) ensure that the connection is strong.

As the number of transistors on a chip increased over time, it became difficult to use wire bonding since there is a limit to the wire bond density. Too many wire bonds decreased reliability and packaging yield and was too expensive.

Question 10

What is tape-automated bonding?

Answer 10

In this type of bond pad to package connection, the die is bonded to a flexible polyamide substrate and lithography is used to make I/O connections. This was the first type of bond pad to package connection to use solder bumps.

Question 11

What are solder bumps? How are they created?

Answer 11

Solder bumps are rounded or pillar like bumps of Sn/Pb alloy (50/50 or eutectic) that are used to connect the bond pad to the package. The alloy was chosen for its low melting point and good conductivity but lead-free options are coming into use, such as Cu pillars.

The solder bumps are placed on a bonding pad with several layers that prevent the solder from entering the die and provide mechanical support.

The material is deposited using sputtering, lithography/etch is used to separate individual bumps, and then reflow is used to create the bump shape. The shape has good thermal conductivity.

Question 12

What is flip-chip?

Answer 12

Flip chip is a method of packaging that has an array of connectors.

The die is prepared by metallizing the bonding pads and then placing solder bumps on them. Then, the chip is flipped over and placed on the connector array. Hot-air reflow is used to melt the bumps and then the area between the bumps is filled with an electrically insulating glue.

Question 13

What are the advantages and disadvantages of flip chip?

Answer 13

The main advantage is that the entire chip can be used for interconnects, not just the outside edge. Also, the process has relatively few steps (all the connections are made at once).

The disadvantage is that cooling is more difficult, it must be via the solder bumps or the back of the chip.

Question 14

What is package-on-package?

Answer 14

A method of packaging more than one element. Separate packages (for memory, logic, etc) are stacked on top of one another. The packages are connected by solder bumps.

Question 15

What are TSVs?

Answer 15

TSV = through silicon via. This technology allows for the highest possible number of interconnects, and allows dice to be stacked on one another.

TSVs are vias that go through the die.

Question 16

What are the advantages of TSVs?

Answer 16

TSVs allow for 3-D architecture of elements that combine logic and memory. This reduces power consumption, reduces element size, increases speed/performance

Question 17

What is the main disadvantage of TSVs?

Answer 17

There are many engineering issues with manufacturing TSVs that have not yet been solved, such as heat management. Also, every new fabrication process represents significant investment and TSVs are not necessarily cost effective (yet)

Question 18

What are silicon interposers?

Answer 18

Silicon interposers are Si chips that can be used to connect different elements in a multi die/multi element board. The interposer transmits electrical signals between elements and connects to the outside.

Question 19

What are the advantages presented by Si interposers?

Answer 19

This is a good solution for multi-element packaging that does not require TSVs, so multi-element devices can be manufactured more simply.

Silicon interposers are makes it easier to incorporate different package elements since the interposer layer can be used to re-distribute signals.

Also, the interposers mean that the die does not have to be planned with space for TSVs, which “waste” chip space.

Question 20

What is 2.5D?

Answer 20

A multi-element packaging strategy that uses Si interposers that have TSVs between die in order to create stacked packages. This is a good alternative to 3-D with TSVs. This is important since stacking allows the fastest memory bandwidth which is for increasing importance.

Question 21

What is EMIB?

Answer 21

Embedded multi-die interconnect bridge

This is a multi-element packing strategy where the different elements are connected via “bridges”. These have several advantages over 2.5D packaging:

Scaling - more flexibility in die placement
Better power distribution, which improves heat dissipation
Better yield
Saves space

Question 22

What is fan-out?

Answer 22

The known good die are placed face-down on a carrier wafer and molded in place. The bonded layer is thinned to and a redistribution layer with bumps on the active face. Then, the die are separated (after packaging).

Question 23

What is encapsulation?

Answer 23

After the packaging connections are created, the entire assembly must be sealed in some way. Ceramics or plastics are traditionally used.