Device Interconnects

Question 1

What is the advantage of multi-layer metalization?

Answer 1

Metallization is required to connect all the transistors. Since the metal interconnects cannot cross, if they are spread out on a single level, they would take up a lot of space. Multi-level metallization, separated by inter-level dielectric, saves chip space and minimizes the wire length required. This makes the chip faster.

Question 2

Why are the higher levels of metallization thicker?

Answer 2

Several reasons:

1. These are global interconnects that run across the chip - at higher levels in the chip, the interconnects connect transistors that are farther from one another, so they must be longer.

Since increasing the length of an electrical component increases the resistance, the pitch is increased as well in order to keep the resistance low.

2. Large dimensions are easier to achieve. Since the cost of failure at this late stage is very high, these interconnects are designed to be easy to manufacture

Question 3

What controls chip speed?

Answer 3

1. Transistor switching speed

2. How fast signals can travel between transistors, aka interconnect speed

Question 4

What is interconnect delay?

Answer 4

The interconnect delay, also known as the RC delay, is the length of time it takes a signal to travel through the interconnects between transistors.

We can calculate the interconnect delay for the intra-level contacts or for the inter-level contacts; the total RC delay depends on both.

Question 5

What parameters influence the inter-level RC delay?

Answer 5

Metal resistivity, dielectric constant of the oxide, wire length, thickness of metal and oxide

Question 6

What parameters influence the intra-level RC delay?

Answer 6

Metal resistivity, dielectric constant of the oxide, interconnect width (line width) and space between interconnects (space width)

Question 7

How can RC delay be minimized without changing interconnect geometry?

Answer 7

1. Lower the resistivity of the metal - this is the motivation behind the move form Al metallization to Cu metallization
2. Lower the dielectric constant of the oxide through the use of “low K oxides”

Question 8

What low-k dielectrics are used as interconnect dielectrics? What are the issues with them?

Answer 8

1. Fluorinated silicon oxide reduces the dielectric from ~4 to ~3.5
2. Carbon-doped oxides with k ~3
3. Polymers with k ~2-2.7, but they lack mechanical strength, chemical resistance, and stability
4. Air is the best low-k dielectric with k = 1, but this represents an engineering challenge
5. MSQ, HSQ - silicon oxides with open structures

Question 9

What are porous dielectrics?

Answer 9

One strategy for incorporating air into the dielectric in order to reduce the RC delay is the use of porous dielectrics. For a small pore percentage, the pores can be random, but as the percentage grows they must be engineered as discrete gaps for the dielectric to be reliable.

Question 10

What are strategies for incorporating air as a low-k dielectric? What are the issues with these strategies?

Answer 10

1. Floating wires - poor reliability, difficult to manufacture
2. Pores - good for small amounts of pores, affects reliability as the pore percentage increases
3. Air gaps engineered using CVD

Question 11

How can RC delay be decreased by changing the chip geometry?

What issues exist with each strategy? When are they used?

Answer 11

1. Increase the thickness of the metal and/or oxide, which decreases the resistance. This increases the interconnect topography and is normally used only in the upper layers of the metallization. The metal and oxide are made both thick and wide to prevent the aspect ratio from increasing.
2. Increasing the metal pitch (line-width + space-width). This increases the space required for metallization and results in a need for more layers
3. Reduce the wire length by adding “pass transistors”. This is worth doing when the interconnect delay is greater than twice the transistor delay. This solution also takes up additional chip space and cost.