OS Design and goals Flashcards
Mainframe Computer goals
Maximum hardware resource utilization
PC
Optimized around a user and it’s programs
Handheld
Easy UI, performance and energy efficiency
Kernel
The programs that run Indefently in the system. All other programs are user or application programs.
Firmware
Program that provides low level control for the hardware
BIOS
Basic Input Output System: non-volatile firmware that is used to perform hardware initialization during the booting process (bootstrapping)
Bootstrapping
Self-starting process. Loaded when the computer is turned on and is stored in ROM or EPROM. Initializes all computer hardware and finally loads the OS kernel and transfers control to it.
Interrupt
A signal sent to the CPU, generated from a hardware device.
Once an interrupt is received alongside its interrupt number, the CPU looks up the Interrupt Vector/Descriptor Table to find the program’s address, loads, and runs it. Also saves the PC, PSW, and registers into the system stack.
Trap
A program generated interrupt for handling requests like direct OS calls and errors.
Synchronous vs Asynchronous I/O handling
Sync:
A trap is set for the IO request. The kernel requests the operation from the device. The Program is marked as blocked. Once the interrupt from the device is complete, the program is marked as ready and will be scheduled to continue execution.
Async:
A trap is set for the IO request. The program continues to run instantly. Basically it can do whatever it wants and will check for the IO result on its own.
When IO is complete, the kernel will wither:
1. Send a signal SIGIO
2. Call a callback
3. update status table
Device-State Table
Used in Async and multi-processor Sync IO to manage device status and IO queue.
DMA
Direct Memory Access:
Allows hardware devices to transfer data from and to the main memory without CPU interference.
DMAC
Direct Memory Access Controller:
Programmed by the CPU when an IO is needed. The controller is programmed with how much data should be written, where to store it (address), and the device data it will communicate with. Takes control of BUS when needed to write to memory.
DMA IO flow
CPU programs DMAC. Orders device controller how much data to send and through what DMA channel. DMAC does its thing and writes to memory. When DMAC sees that it received the amount of data it was supposed to, it creates an interrupt.
Mode Bit
A physical bit in the CPU registry that indicates the current execution mode (User/Kernel)
0 = kernel mode
1 = system mode
