Module 5 - Microprocessor Operation Flashcards

1
Q

Von Neumann Architecture

A
  • Single bus transfers data and program instructions. This means two fetch operations.
  • Slower then Harvard architecture but simpler.
  • Motorolla 68HC11
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2
Q

Harvard Architecture

A
  • Data & program busses are seperate. They each have seperate blocks of memory and seperate busses.
  • Faster (they’re in parallel!), but more complex.
  • PIC Microcontroller.
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3
Q

CISC & RISC

A
  • CISC: Complex Instruction Set Computer.
    • Instructions may take 5+ clock cycles to run (slow), however;
    • Specalized instructioons (therefore less required)
  • RISC: Reduced Instruction Set Computer
    • Few instructions, but they run fast. It’s simplistic.
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4
Q

Bus Systems

A

Three main types of busses:

  • Address: uni-directional
  • Data: bi-directional (all data in and out of CPU)
  • Control: many control lines, i.e.
    • clock signals
    • CPI control signals to bus-connected devices (read/write, etc…)
  • ROM - program INSTRUCTIONS!
  • RAM - program DATA!
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5
Q

Operation Code

A
  • AKA OPCODE
  • Made up of binary numbers
  • Includes “OPCODE” field (refers to actual operation), as well as the “register address” field (where the operation is!)
  • I.e. “ADD” - 1001101
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6
Q

Program Counter

A
  • Keeps track of the program sequencing by storing the address of the current program instruction being exectued.
  • When powered on, PC = 0, but when a program is executed, the PC counter counts sequentially up.
  • Special control words/operations occupy the first few address busses, so PC counter may have to jump from 0 to the first instruction code.
  • A stack is a temporarily PC store for the instruction code of a subroutine. It’s stored for later use.
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7
Q

Instruction Register

A
  • To actually execute an instruction, the processor copies the instruction code** from **program memory** to the **instruction register.
  • The instruction must the be decoded the Instruction Decoder. This is a combinational logic circuit that looks at the instruction code, and works out where it wants to go.
  • For example, some code comes through, the instruction decoder reads it, notices it wants to go to some register, and takes care of the data bus & control lines to send it there.
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8
Q

Control Unit

A
  • Sequential logic block (i.e. flip flops);
  • Sends signals to ports to move data around the chip;
  • AKA Instruction Decoder (it decodes the instructions, and decides what should be done next);
  • Clock signals ensure it runs programs sequentially (powered by a crystal oscilator);
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9
Q

Interrupt

A
  • An instruction code that’s like an alternative to physically resetting a device.
  • Interrupts are signals that are generated to force a change in operation sequence.
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10
Q

Arithmetic Logic Unit (ALU)

A
  • General purposes logic unit that can calculate stuff (arithmetic and boolean functions).
  • Combines information from working register/accumulator as well as an operand register (registers where the two values are stored) and then adds/subtracts them.
  • The working register is not only the source of one of the operands, but it is also the destination of the result.
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11
Q

Assembly Language Syntax form

A
  • Label: user defined, i.e. “BILL”
  • Mnemonic: operation/instruction, i.e. “MOVLW (move)”
  • Operand: memory address/register bit/destination - will cover later.
  • Comments: “set counter”, or “if zero…”
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12
Q

Numbers in assembly language

A
  • Binary: B’1001001’
  • Hex: H’3F’
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