Logic Families Flashcards
Understand TTL & CMOS circuits and characteristics
TTL (definition)
Transistor-transistor logic
What are some uses of a transistor?
a) a switch
b) an amplifier
How would one use a transistor as a switch?
source a small current into the base; this will allow a much larger current to flow from the collector to the emitter (conventional current flow)
What is a multiple-emitter transistor and how does it work?
Literally multiple bits of ‘N’ emitters (in the case of an NPN transistor) instead of just one.
If both emitters = 1 (logic high), emitter-collector current flows
If either emitter = 0 (logic low), no emitter-collector current flows
How would one disable an output of logic TTL circuit if, say, multiple outputs of a NAND gate must form one single output?
Have a third emitter ‘input’ on the input transistor instead of just one. Therefore, if it = 0 (logic low), output is automatically 0 (high impedance, disabled)
Why are schottky diodes used in TTL logic gates?
Say we’re switching an inductive load with a transistor… When we turn it off, the inductor tries to keep current the same and thus produces back EMF. This could kill the transistor!
Solution? Forward bias diode prevents back current. Why schottky?
a) smaller V(forward bias) = 0.2V instead of 0.7V
b) switches faster as V(forward bias) keeps transistor just below saturation
What is a ‘noise margin’?
Input signals aren’t always ideal. Instead of being square waveforms (+5V – 0V – +5V), there is noise which stuffs it (+4V, +4.1V, +4.8V –). Noise margin is the minimum and maximum Vin values that will be read as a ‘1’ or ‘0’
What is ‘fan-out’?
max number of digital inputs a logic gate gate feed
Fan out for TTL
10
What are some practical issues with TTL?
current spikes due to capacitive loads; unused inputs left floating picking up noise; switch bounce
What may be an issue when switching a capacitive load with TTL, and how may it be prevented?
Current spikes when switching (charge/discharge of capacitor).
Prevent by placing a de-coupling capacitor (0.01uF - 0.1uF) every ~5 gates.
Why are floating inputs an issue, and how may this be resolved?
unused inputs left ‘floating’ (not connected to anything) may pick up noise.
ALWAYS connect unused inputs either to ground or to the power rail via a 1k resistor (whichever gives desired logic result)
Tell me some stand-out features of CMOS logic…
a) it’s a little slower than TTL
b) super, super low power consumption due to high input resistance
c) good noise immunity
d) wide variety of Vin (~3-15V)
e) very susceptible to static electricity
Tell me about power consumption on CMOS chips
dissipation is low and is due to leakage current only
What are the sources of leakage current on a CMOS chip?
dynamic dissipation (during changes of state) - power lost in charging/discharging capacitive loads. This energy increases as frequency increases. A 'through-current' dissipation when the 'N' and 'P' type semiconductors conduct simultaneously. The longer the rise/fall time of the signal, the longer this happens.
