Module 5 Flashcards

1
Q

Input Output Techniques -> Programmed Input Output

A

Overview of Programmed I/O:
Programmed I/O is an input/output method where the CPU has complete control over data transfer between the CPU and the peripheral devices.
The CPU directly executes a program to initiate, direct, and terminate the I/O operation.

Characteristics:
All steps of the I/O operation are controlled by the CPU.
The method is simple and hardware cost-effective because no additional controllers or complex I/O modules are required.
However, this comes at the cost of efficiency because the CPU has to wait for the I/O module to complete operations, wasting time.

Steps in Programmed I/O:
Step 1: The CPU checks the status of the I/O device using a status bit.
Step 2: It tests whether the device is ready or not. If the device is not ready, the CPU repeats the process.
Step 3: If the device is ready, the CPU requests data transfer.
Step 4: The I/O module performs the transfer and sends the data to the CPU, which stores it in memory.

Drawbacks:
Inefficient CPU Usage: The CPU spends time repeatedly polling the status bit instead of performing other tasks.
Wasted Time: If the device is not ready, the CPU must wait and cannot proceed with other computations.

Details of Programmed I/O Operations:
The CPU periodically checks status bits set by the I/O module.
The I/O module does not interrupt the CPU. Instead, the CPU must check the status periodically (polling).
The CPU either waits or retries after some delay if the I/O operation is not ready.

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2
Q

Input Output Techniques -> Interrupt Driven Input Output

A

Overview of Interrupt Driven I/O (Slide 1):
Problem in Programmed I/O: It leads to “busy waiting,” where the CPU continuously checks if the I/O device is ready, wasting valuable processing time.
Interrupt-Driven I/O Solution:
- The CPU can switch to another task when the I/O device is not ready.
- The I/O module sends an interrupt signal to the CPU when it is ready, eliminating the need for constant checks.

Advantages of Interrupt Driven I/O (Slide 2):
Avoids CPU Waiting: The CPU doesn’t waste cycles checking the I/O device status.
Event-Driven Communication: The I/O module signals the CPU only when it is ready, improving efficiency.
Better Performance: It allows the CPU to perform other tasks while waiting for I/O.

Basic Operation (Slide 3):
Steps in Interrupt Driven I/O:
- CPU issues a read command to the I/O module for data.
- The I/O module retrieves data from the peripheral device while the CPU continues with other operations.
- The I/O module interrupts the CPU once the data is ready.
- The CPU processes the interrupt, requests the data, and the I/O module transfers the data to the CPU.

CPU Viewpoint (Slide 4):
Steps for Handling Interrupts:
The CPU issues a read command and continues with other instructions.
It periodically checks for interrupts at the end of each instruction cycle.
When interrupted, the CPU:
- Saves its current context (registers, etc.).
- Processes the interrupt, fetches the data, and stores it.

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3
Q

Input Output Techniques -> Direcct Memory Access

A

What is DMA?
- DMA allows devices to directly transfer data between memory and peripherals without requiring continuous CPU intervention. This overcomes the limitations of programmed and interrupt-driven I/O by reducing the burden on the CPU.

Key Components of DMA:
- DMA Controller: A hardware module responsible for managing the data transfer process.
- CPU Interaction: The CPU initializes the DMA operation, specifying details like the starting address, the amount of data to transfer, and whether the operation is a read or write.
- Independence: After initialization, the DMA controller takes over, enabling the CPU to continue other tasks.

DMA Operations:
- The CPU provides the necessary instructions (read/write, device address, memory address, and data size) to the DMA controller.
- The DMA controller handles the transfer and notifies the CPU once the process is complete using an interrupt.
- This process allows simultaneous data transfer and CPU execution of unrelated tasks.

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4
Q

Modes of DMA Transfer

A

Burst Mode:
- Transfers a block of data at a high speed in a single burst.
- Offers maximum throughput but monopolizes the bus during the transfer.

Cycle Stealing Mode:
- Transfers one data word at a time, momentarily “stealing” the bus from the CPU.
- Balances CPU operation and data transfer.

Transparent Mode:
- Transfers data only during idle CPU cycles.
- Ensures minimal CPU interference but reduces overall throughput.

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5
Q

Adv and Disadv of DMA

A

Advantages
- High Transfer Rates:
Fewer CPU cycles are consumed per transfer.
Memory operations are faster as the CPU is bypassed.

  • Reduced CPU Workload:
    Frees up CPU cycles for other processes.

Disadvantages
- Requires Dedicated Hardware:
DMA controllers add cost and complexity to the system.

  • Synchronization Challenges:
    Cache coherence issues arise if the CPU accesses outdated memory data during DMA operations.
  • More Expensive:
    Due to additional hardware requirements (e.g., the DMA controller).
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