Module 4 Flashcards
Explain the units of transfer in memory
1. Internal
Definition: Refers to data transfer within the system (e.g., between the CPU and memory).
Key Factor: Governed by the data bus width, which determines how many bits can be transferred simultaneously.
Example: If the data bus width is 32 bits, the internal unit of transfer is 32 bits.
2. External
Definition: Refers to data transfer between the system and external devices or storage.
Key Factor: Typically involves transferring blocks of data, which are larger than individual words.
Example: Hard drives and SSDs transfer data in blocks rather than one word at a time.
3. Addressable Unit
Definition: The smallest unit of memory that can be uniquely identified and addressed.
In most systems, this is a byte. In some cases, it might be a word, depending on the system’s architecture.
Explain the different access methods
Sequential:
- Start at the beginning and read through in
order
- Access time depends on location of data and
previous location
- e.g. tape
Direct:
- Individual blocks have unique address
- Access is by jumping to vicinity plus
sequential search
- Access time depends on location and
previous location
- e.g. disk
Random:
- Individual addresses identify locations exactly
- Access time is independent of location or
previous access
- e.g. RAM
Associative:
- Data is located by a comparison with contents
of a portion of the store
- Access time is independent of location or
previous access
- e.g. cache
Explain the three key performance metrics of memory
1. Access Time
Definition: The duration between requesting an operation (read or write) and when the data is made available or written at the desired memory location.
Key Point: It’s crucial in determining how quickly the memory can respond to a single request.
2. Memory Cycle Time
Definition: The minimum time between two consecutive memory operations (like read requests). It accounts for the time needed to reset the memory circuitry for the next operation.
Key Point: This metric determines how quickly back-to-back requests can be processed.
3. Transfer Rate
Definition: The speed at which data can be transferred between memory and another component (e.g., CPU or disk).
Key Point: Measured in units like megabytes per second (MB/s), it reflects the efficiency of data movement.
Key physical characteristics of memory
1. Decay
Definition: Refers to how data stored in memory degrades over time if not refreshed or rewritten.
Relevance: Common in volatile memory like DRAM, which requires constant refreshing to maintain data integrity.
2. Volatility
Definition: Indicates whether the memory retains data when power is turned off.
Types:
Volatile Memory: Loses data when power is off (e.g., RAM).
Non-Volatile Memory: Retains data without power (e.g., ROM, Flash memory).
3. Erasable
Definition: Describes whether and how stored data can be erased and rewritten.
Categories:
Non-Erasable: Data is permanent once written (e.g., Masked ROM).
Erasable: Data can be erased and rewritten:
Electrical Erasing: Flash memory.
Optical or UV Erasing: EPROM.
4. Power Consumption
Definition: The amount of power required to operate the memory.
Impact:
Lower power consumption is crucial for mobile and embedded devices.
Non-volatile memory generally consumes less power compared to volatile memory like DRAM.
Explains the Memory Hierarchy, which organizes memory into levels based on speed, cost, and proximity to the CPU
Levels of the Memory Hierarchy
Top Level: Inboard Memory
Components: Registers, Cache, Main Memory (RAM).
Features:
Fastest access speed.
Lowest capacity.
Highest cost per bit.
Examples:
Registers: Store immediate data for CPU instructions.
Cache: Provides fast access to frequently used data.
Main Memory (RAM): Used for currently running programs and data.
Middle Level: Outboard Storage
Components: Magnetic Disks, CDs, DVDs.
Features:
Larger capacity than inboard memory.
Slower access compared to inboard memory.
Lower cost per bit.
Examples:
Hard drives, SSDs, CD-ROMs.
Bottom Level: Off-line Storage
Components: Magnetic Tape, MO (Magneto-optical), WORM (Write Once, Read Many).
Features:
Largest capacity.
Slowest access speed.
Lowest cost per bit.
Examples:
Used for archival and backup storage.
Key Observations
Decreasing Cost: Cost per bit decreases as you move down the hierarchy.
Increasing Capacity: Storage capacity increases at lower levels.
Increasing Access Time: Memory access becomes slower at lower levels.
Explain RAM and its types
1. RAM (Random Access Memory)
Random Access: Any memory location can be accessed directly, not sequentially.
Read/Write: Allows both reading and writing operations.
Volatile: Loses data when power is turned off.
Temporary Storage: Stores data and instructions currently in use.
Types:
Static RAM (SRAM)
Dynamic RAM (DRAM)
* Dynamic RAM (DRAM)
Characteristics
Bits Stored as Charges: Data is stored as electrical charges in capacitors.
Charges Leak: Stored charges dissipate over time.
Needs Refreshing: Requires periodic refresh to retain data, even when powered.
Simpler Construction: Uses fewer components (one transistor and one capacitor per cell).
Less Expensive: More cost-effective than SRAM.
Slower: Access time is slower compared to SRAM.
Main Memory: Commonly used in systems as main memory.
Analog Nature: The charge level determines the stored value (0 or 1).
Structure
A transistor acts as a switch to control access to a storage capacitor, which holds the bit of data.
* Static RAM (SRAM)
Characteristics
Bits Stored as Flip-Flops: Data is stored using bistable circuits (on/off switches).
No Charge Leakage: Data remains intact as long as power is supplied.
No Refreshing Needed: Unlike DRAM, it doesn’t need periodic refreshing.
More Complex Construction: Uses multiple transistors per cell (typically 4-6).
More Expensive: Higher cost per bit due to complexity.
Faster: Faster access times compared to DRAM.
Cache Memory: Commonly used as cache memory in systems.
Digital Nature: Uses stable on/off states.
Difference between SRAM and DRAM
Construction:
SRAM uses flip-flops made of transistors to store data.
DRAM uses a combination of capacitors and transistors.
Speed:
SRAM is faster due to its simpler data access mechanism.
DRAM is slower because it requires accessing and refreshing capacitors.
Refreshing:
SRAM does not need to be refreshed as it retains data as long as power is supplied.
DRAM requires periodic refreshing to maintain the stored data.
Cost:
SRAM is more expensive due to its complex construction.
DRAM is cheaper and more cost-efficient for large memory capacities.
Density:
SRAM is less dense, meaning it requires more space for the same amount of memory.
DRAM is more dense and can store more data in the same physical space.
Power Consumption:
SRAM consumes less power during operation since it doesn’t require refreshing.
DRAM consumes more power because of the refresh cycles.
Usage:
SRAM is typically used for cache memory due to its high speed.
DRAM is used as main memory for larger storage needs.
Data Storage Method:
SRAM stores data in stable on/off transistor states.
DRAM stores data as charges in capacitors, which can leak over time.
ROM and it’s Types
Read-Only Memory (ROM)
Definition: ROM is non-volatile memory used for permanent data storage.
Characteristics:
Non-volatile: Retains data even when the power is turned off.
Can only be read; writing new data is restricted.
Commonly used for firmware or system software.
Types of ROM
1. Programmable Read-Only Memory (PROM)
Initially empty when manufactured.
Can be permanently programmed once by the user.
Limitation: Cannot be erased or reprogrammed.
2. Erasable Programmable Read-Only Memory (EPROM)
Can be programmed, erased, and reprogrammed multiple times.
Erasing Method: Requires ultraviolet (UV) light exposure to erase data.
The chip has a small transparent window to allow UV light to enter.
After reprogramming, the window is sealed to protect data.
Access Time: Around 45–90 nanoseconds.
3. Electrically Erasable Programmable Read-Only Memory (EEPROM)
Can be erased and reprogrammed using electrical signals (no UV light needed).
Requires special machines for reprogramming.
Access Time: Between 45 and 200 nanoseconds.
4. Flash ROM
Similar to EEPROM but with additional flexibility.
Can be reprogrammed while still in the computer.
Commonly used for storing upgradable programs (e.g., BIOS, firmware).
Usage: Found in modems, smartphones, and storage devices.
Access Time: Around 45–90 nanoseconds.
5. ROM Cartridges
Commonly used in gaming machines.
Purpose: Prevents unauthorized copying of software.
Provides fast access to pre-installed programs.
What is Cache memory?
Definition: A small, high-speed memory located between the CPU and main memory (RAM).
Purpose: Stores frequently accessed data and instructions.
Reduces the time the CPU spends waiting for data from the slower main memory.
Location: Can be embedded in the CPU (on-chip) or on a separate module.
Data Transfer:
Word Transfer: For individual pieces of data.
Block Transfer: For larger memory blocks.
Levels of Cache
Level 1 (L1) Cache:
Smallest and fastest.
Embedded directly within the processor chip.
Handles the most frequently used instructions and data.
Level 2 (L2) Cache:
Larger than L1, but slower.
May be located on the CPU chip or a separate coprocessor.
Provides additional caching for data not found in L1.
Level 3 (L3) Cache:
Specialized cache to improve the performance of L1 and L2.
Larger than L1 and L2 but slower.
Typically shared across multiple cores in multi-core processors.
Still faster than main memory.
Cache Operation Overview
CPU Request:
The CPU requests data from a specific memory location.
Cache Check:
The cache checks if the requested data is already stored in it (called a cache hit).
If present, the data is retrieved quickly.
Cache Miss:
If the data is not found, the cache fetches the required block from the main memory and stores it for future use.
Tags:
Used to identify which block of main memory is stored in each cache line.
Cache Coherence
Cache Coherence
Problem:
Multiple copies of the same data may exist in different caches in a multiprocessor system.
This can lead to inconsistent data if one processor modifies a value while others read outdated copies.
Solutions:
Write Through: Data written to the cache is also updated in the main memory simultaneously.
Write Back: Updates are made in the cache first and written to main memory only when the cache line is replaced.
Write Invalidate: When a processor writes, other processors’ cache copies of that line are invalidated.
Write Update: Updated data is distributed to all caches holding that data.
Hardware and Software solutions for problems with Cache Coherence
Software Solutions
Approach:
Compiler and Operating System manage cache-related issues.
Overhead: Cache coherence management is moved to compile time, reducing runtime complexity.
Key Steps:
Compiler marks data likely to change, ensuring the OS avoids caching such data.
Shifts design complexity from hardware to software.
Hardware Solutions
Cache Coherence Protocols:
Ensure all processors have a consistent view of memory.
Dynamic recognition of conflicts or inconsistencies at runtime.
Snoopy Protocols:
Cache controllers monitor shared data and announce changes to other caches.
Effective in bus-based multiprocessor systems.
Advantages:
Transparent to the programmer.
Efficient use of cache resources.
Snoopy Protocols
Snoopy Protocols
Concept:
Cache controllers handle coherence.
When a line is shared among caches, updates are broadcast to maintain consistency.
Characteristics:
Designed for multiprocessor systems.
Increases bus traffic due to frequent announcements of changes.
Write Through, Write Back, Write Update and Write Invalidate
Write Through
Mechanism:
All write operations update both the cache and the main memory simultaneously.
Pros:
Maintains memory consistency across processors.
Cons:
High traffic between cache and memory.
Slower write operations.
Write Back
Mechanism:
Updates are made in the cache first.
Main memory is updated only when the cache line is replaced.
Details:
Cache lines have an update bit to indicate modified data.
Reduces traffic to main memory but can lead to out-of-sync caches.
Write Update
Mechanism:
When a value is updated in a cache, the updated value is propagated to all other caches.
Advantages:
Ensures immediate consistency across caches.
Challenges:
Requires more bus traffic to broadcast updates.
Write Invalidate
Mechanism:
When a processor writes to a cache line, all other copies of that line in other caches are invalidated.
The writing processor gains exclusive access to the data.
MESI Protocol:
Cache line states: Modified, Exclusive, Shared, Invalid.
