Module 1-3 Flashcards
Difference between Computer Organisation and Architecture
Computer Architecture:
* Focuses on how hardware parts are linked to work together inside a computer
* Bridge between hardware and software
* Programmers see it through instructions, addressing modes and registers
* Its a higher level of design
* Comes first while planning out a system
Computer Organisation
* Looks into how the system is built physically
* It deals with how the parts are arranged and organised
* Lower level of design, deals with adders subtractors, registers etc
* Its the practical realization of the architecture
* Organisation follows architecture
What is a Bus?
A communication pathway connecting two or more devices
For Ex: A bus enables a computer processor to communicate with the memory or video card to communicate with the memory
- There are a number of possible interconnection
systems - Single and Multiple bus structures
- Control/Address/Data Buses.
Have following major functions:
* Data Sharing: Serial/Parallel buses, 8, 16, even 32 bits.
* Addressing: Has address lines to send data to from memory locations
* Power: Can be used to supply power to various peripherals
* Timing: System clock synchronise the peripherals attached to it with the rest of the system.
Explain the Von Neumann Concept
The Von Neumann architecture is based on the stored-program concept, which means that program instructions and data are stored in the same memory.
Main Memory
Stores programs and data in binary form.
Accessible to both the Central Processing Unit (CPU) and Input/Output devices.
Data and instructions are retrieved from memory as needed for processing.
Arithmetic Logic Unit (ALU)
Performs all arithmetic and logical operations (e.g., addition, subtraction, AND, OR).
Operates on binary data provided by memory or other parts of the CPU.
Control Unit
Directs the operation of the processor.
Fetches instructions from memory, decodes them, and executes them by coordinating with the ALU and other components.
Input and Output Equipment
Input devices (e.g., keyboard, mouse) feed data into the system.
Output devices (e.g., monitor, printer) present processed data to the user.
The control unit manages data transfer between the CPU and these devices.
Types of Buses
Dedicated
* Separate data and address lines
Multiplexed
* Shared lines
* Address valid or data valid control lines
* Advantage: Fewer lines
* Disadvantage: Complex controls, ultimate performance
Bus Arbitration
Types:
Central: Only a single bus arbiter or controller, this arbiter determines which device gets access to the bus at what times.
Distributed:The devices themselves coordinate and have embedded logic to determine who gets to control the bus at any given moment.
PCI bus
Peipheral Component Interconnect
Direct Memory Access (DMA): PCI allows devices to access the system memory directly, which speeds up data transfer.
Plug and Play (PnP): Intel added PnP functionality to PCI, making it easier for the system to recognize and configure new devices automatically.
PCI Bus Lines (Required)
System Lines:
Include essential control signals like clock and reset to synchronize all connected devices.
Address & Data:
32 Multiplexed Lines: These lines are shared for both address and data transmission, reducing the number of physical lines required.
Interrupt & Validate Lines: Ensure proper data validation during operations.
Interface Control:
Manages the interaction between devices, ensuring commands are issued and executed in an orderly fashion.
Arbitration:
Arbitration is not shared, meaning each device has direct communication with the bus arbiter to prioritize and manage data flow.
Error Lines:
Provide mechanisms for error detection and correction, ensuring reliable communication between components.
SCSI Bus
Small Computer System Interface
It’s a fast bus designed to have multiple devices connect to a system simultaneously. Devices like hard disks, printers, scanners etc.
Adv:
* Allows multiple devices to connect on the same bus
* Very versatile across different types of systems
* Backwards compatible in generations
Disadv:
* Requires manual BIOS setup
* No standard software interface to manage/configure the bus.
* Many types with varying speeds/bandwidth making it difficult to choose one for self.
Tasks a CPU must do
Fetch instructions - reads an instruction from memory
Interpret instructions - instruction is decoded to determine what action is required.
Fetch data - The execution of an instruction may require reading data from memory or an I/O module
Process data - The execution of an instruction may require performing some arithmetic or logical operation on data
Write data - the results of an execution may require writing data to memory or an I/O module.
Explain the Control and Program Status registers
* Memory Access Register
Connected to Address bus
Specifies address for read or write operation.
* Memory buffer register
Connected to data bus
Holds data to write, or last data read
* Program Counter
Holds address of next instruction to be fetched
* Instruction register
Holds last instruction fetched/current instruction being executed.
The 32-bit instruction pointer register and the 32-bit flags register combined are considered as the control registers.
Many instructions involve comparisons and mathematical calculations and change the status of the flags and some other conditional instructions test the value of these status flags to take the control flow to other location.
List and explain the bits inside a PSW register
- Sign: Contains the sign bit of the result of the last arithmetic operation.
- Zero: Set when the result is 0.
- Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a high-order bit. Used for multiword arithmetic operations.
- Equal: Set if a logical compare result is equality.
- Overflow: Used to indicate arithmetic overflow.
- Interrupt Enable/Disable: Used to enable or disable interrupts.
- Supervisor: Indicates whether the processor is executing in supervisor or user mode. Certain privileged instructions can be executed only in supervisor mode, and certain areas of memory can be accessed only in supervisor mode.
General Registers
AX is the primary accumulator; it is used in input/output and most arithmetic instructions. For example, in multiplication operation, one operand is stored in EAX or AX or AL register according to the size of the operand.
BX is known as the base register, as it could be used in indexed addressing.
CX is known as the count register, as the ECX, CX registers store the loop count in iterative operations.
DX is known as the data register. It is also used in input/output operations. It is also used with AX register along with DX for multiply and divide
operations involving large values.
Pointer Registers
Instruction Pointer (IP) − The 16-bit IP register stores the offset address of the next instruction to be executed. IP in association with the CS register (as CS:IP) gives the complete address of the current instruction in the code segment.
Stack Pointer (SP) − The 16-bit SP register provides the offset value within the program stack. SP in association with the SS register (SS:SP) refers to be current position of data or address within the program stack.
Base Pointer (BP) − The 16-bit BP register mainly helps in referencing the parameter variables passed to a subroutine. The address in SS register is combined with the offset in BP to get the location of the parameter. BP can also be combined with DI and SI as base register for special addressing.
Index Registers
SI and DI, are used for indexed addressing and sometimes used in addition and subtraction.
There are two sets of index pointers −
Source Index (SI) − It is used as source index for string operations.
Destination Index (DI) − It is used as destination index for stringoperations.
Condition Code (Flag) Register Bits
Overflow Flag (OF) − It indicates the overflow of a high-order bit (leftmost bit) of data after a signed arithmetic operation.
Direction Flag (DF) − It determines left or right direction for moving or comparing string data. When the DF value is 0, the string operation takes left-to-right direction and when the value is set to 1, the string operation takes right-to-left direction.
Trap Flag (TF) − It allows setting the operation of the processor in single-step mode. The DEBUG program we used sets the trap flag, so we could step through the execution one instruction at a time.
Sign Flag (SF) − It shows the sign of the result of an arithmetic operation. This flag is set according to the sign of a data item following the arithmetic operation. The sign is indicated by the high-order of leftmost bit. A positive result clears the value of SF to 0 and negative result sets it to 1.
Zero Flag (ZF) − It indicates the result of an arithmetic or comparison operation. A nonzero result clears the zero flag to 0, and a zero result sets it to 1.
Interrupt Flag (IF) − It determines whether the external interrupts like keyboard entry, etc., are to be ignored or processed. It disables the external interrupt when the value is 0 and enables interrupts when set to 1.
Auxiliary Carry Flag (AF) − It contains the carry from bit 3 to bit 4 following an arithmetic operation; used for specialized arithmetic. The AF is set when a 1-byte arithmetic operation causes a carry from bit 3 into bit 4.
Parity Flag (PF) − It indicates the total number of 1-bits in the result obtained from an arithmetic operation. An even number of 1-bits clears the parity flag to 0 and an odd number of 1-bits sets the parity flag to 1.
Carry Flag (CF) − It contains the carry of 0 or 1 from a high-order bit (leftmost) after an arithmetic operation. It also stores the contents of last bit of a shift or rotate operation.
Segment Registers
Segments are specific areas defined in a program for containing data, code and stack. There are three main segments −
Code Segment − It contains all the instructions to be executed. A 16-bit Code Segment register or CS register stores the starting address of the code segment.
Data Segment(DS,ES) − It contains data, constants and work areas. A 16-bit Data Segment register or DS register stores the starting address of the data segment.
Stack Segment − It contains data and return addresses of procedures or subroutines. It is implemented as a ‘stack’ data structure. The Stack Segment register or SS register stores the starting address of the stack.
Addressing modes
- Immediate Addressing
The operand is directly provided in the instruction.
Example: MOV AX, 5
Why? It’s the simplest mode and widely used for constant data. - Register Addressing
The operand is in a register.
Example: MOV AX, BX
Why? It’s very fast since data is accessed from registers. - Direct Addressing
The instruction contains the memory address of the operand.
Example: MOV AX, [1234h]
Why? It’s a foundational memory addressing mode, used to access fixed memory locations. - Indirect Addressing
The address of the operand is stored in a register or memory.
Example: MOV AX, [BX]
Why? Essential for accessing dynamic data locations. - Indexed Addressing
Combines a base address with an index register.
Example: MOV AX, [SI+1234h]
Why? Used for array and sequential data access, common in loops. - Based Addressing
Uses a base register with a fixed offset.
Example: MOV AX, [BX+Offset]
Why? Helps in accessing memory relative to a known base location. - Based Indexed Addressing
Combines a base register, an index register, and optionally a displacement.
Example: MOV AX, [BX+SI+10h]
Why? Adds flexibility for accessing complex data structures. - Relative Addressing
Calculates the address relative to the Program Counter (PC).
Example: JMP +5
Why? Used in branching and control-flow instructions. - Stack Addressing
Operands are accessed using the stack pointer (SP) or base pointer (BP).
Example: PUSH AX, MOV AX, [BP+4]
Why? Critical for subroutine calls, parameter passing, and temporary storage.
Short note on instruction formats
Layout of Bits in an Instruction:
The instruction format defines the number and position of bits assigned to each part of an instruction (e.g., opcode, operands).
For example, in an instruction like MOV AX, BX, bits are allocated to identify MOV as the opcode and AX and BX as operands.
Includes Opcode:
The opcode specifies the operation that the CPU should perform (e.g., MOV, ADD, JMP).
It’s a specific binary code within the instruction that tells the CPU what action to execute.
Includes Explicit or Implicit Operands:
Explicit operands are directly specified in the instruction (e.g., MOV AX, BX where AX and BX are explicit operands).
Implicit operands are not explicitly stated but are implied by the instruction (e.g., in INC AX, AX is implicitly the operand to be incremented).
Usually More than One Instruction Format in an Instruction Set:
Most instruction sets have multiple formats to support different types of operations.
For example, there may be separate formats for register-to-register operations, memory access operations, and immediate (constant value) operations.
Having different formats allows the CPU to optimize the handling of various instruction types efficiently.
Short note on the factors affecting the length of an instruction
Memory Size: More memory requires longer instructions to address all locations.
Memory Organization: Byte-addressable memory may need more bits than word-addressable.
Bus Structure: Wider buses handle longer instructions faster; narrow buses may slow down instruction transfer.
CPU Complexity: Complex CPUs support complex instructions, often needing more bits; simpler CPUs use fewer bits.
CPU Speed: Longer instructions can slow down fetching and decoding; shorter instructions are faster but limit operations.
Short note on factors influencing allocation of bits
Register versus memory - A machine must have registers so that data can be brought into the processor for processing. The more that registers can be used for operand references, the fewer bits are needed
Number of register sets - Some architectures, including that of the x86, have a collection of two or more specialized sets (data & addressing). a functional split requires fewer bits to be used in the instruction.
Address range - the range of addresses that can be referenced is related to the number of address bits. it is still convenient to allow rather large displacements from the register address, which requires a relatively large number of address bits in the instruction.
Address Granularity - In a system with 16- or 32-bit words, an address can reference a word or a byte at the designer’s choice. Byte addressing is convenient for character manipulation but requires, for a fixed size memory, more address bits.
Instruction Cycle
Fetch:
The CPU retrieves the instruction from memory.
This step determines what the CPU will do next.
Indirect (Decode):
The instruction is analyzed (decoded) to understand what needs to be done.
If the instruction refers to additional memory locations (like data to work with), those addresses are accessed here.
Execute:
The CPU performs the operation specified by the instruction, such as addition, subtraction, or moving data.
Interrupt:
If an external or internal event requires attention (e.g., input from a keyboard), the CPU temporarily stops the current process and handles the event.
Afterward, it resumes the instruction cycle.
Explain the Fetch cycle
Beginning:
The Program Counter (PC) holds the address of the next instruction.
Step 1:
The address in the PC is moved to the Memory Address Register (MAR). This connects the address to the system bus.
Step 2:
- The MAR address is placed on the address bus, and the control unit issues a READ command.
- The data from the address is loaded into the Memory Buffer Register (MBR).
- The PC is incremented by one for the next instruction.
Step 3:
The content of the MBR is moved to the Instruction Register (IR), where it will be decoded and executed.
Fetch Sequence (Symbolic):
t1: MAR ← PC
t2: MBR ← MEMORY(PC), PC ← PC + 1
t3: IR ← MBR
Explain the Indirect/Decode Cycle
Step 1:
The address field of the Instruction Register (IR) is moved to the Memory Address Register (MAR) to fetch the address of the operand.
Step 2:
The address in the IR is updated with the contents from the Memory Buffer Register (MBR). This changes the addressing to direct rather than indirect.
Step 3:
Now, the IR holds the operand’s direct address, as if no indirect addressing had been applied.
Indirect Cycle (Symbolic Sequence)
t1: MAR ← IR(Address)
t2: MBR ← MEMORY(MAR)
t3: IR(Address) ← MBR
Explain the Execute cycle
A concise explanation of the Execute Cycle for an ADD instruction:
For ADD R1, X, which adds the contents of memory location X to register R1 and stores the result in R1:
t₁: IR → MAR
Move the address from the Instruction Register (IR) to the Memory Address Register (MAR).
t₂: MEMORY → MDR
Load the data from the memory location specified by MAR into the Memory Data Register (MDR).
t₃: MDR + R1 → R1
Add the content of MDR to R1 and store the result back in R1.
Explain the Interrupt cycle
Step 1:
The contents of the Program Counter (PC) are transferred to the Memory Buffer Register (MBR) to be saved for returning after the interrupt.
Step 2:
The Memory Address Register (MAR) is loaded with the address to save the PC value.
The PC is then updated with the address of the interrupt-processing routine’s start.
Step 3:
The MBR, which holds the old PC value, is stored in memory.
Symbolic Sequence
t₁: MBR ← (PC)
t₂: MAR ← SAVE_ADDRESS, PC ← ROUTINE_ADDRESS
t₃: MEMORY ← (MBR)
Short note on Micro operations
Micro-Operations
Micro-operations are the small, atomic steps that make up each stage of the fetch/execute cycle in a CPU.
Each instruction cycle includes several micro-operations, performing minimal actions to process data.
Types of Micro-Operations
Register Transfer: Moves data between internal registers.
Memory Transfer: Transfers data between registers and external memory.
Input/Output Transfer: Transfers data between registers and I/O devices.
Arithmetic or Logical Operations: Performs calculations or logical operations within the CPU.
Functional Requirements of the Control Unit
- Define the basic elements of the processor.
- Describe the micro-operations that the processor performs.
- Determine the functions that the control unit must perform to cause the micro-operations to be performed.
Implementation of a Control Unit
Implementation of Control Signals
Control Signal Generation:
Each control signal is represented as a bit (on/off).
Control words represent sets of micro-operations required by each instruction.
Control Words and Sequences:
Each micro-operation has an associated control word.
A sequence of control words defines the steps for a complete machine code instruction.
Address for Next Instruction:
Control words may include an address to indicate the next microinstruction, depending on certain conditions.
Input in of the Control Unit
Clock: Keeps time for the control unit, triggering one or multiple micro-operations per clock pulse, also known as the processor cycle time or clock cycle time.
Instruction Register: Holds the opcode and addressing mode of the current instruction, guiding which micro-operations to perform in the execute cycle.
Flags: Indicate the processor status and outcomes of previous ALU operations. For instance, the zero flag in an ISZ instruction prompts the control unit to increment the PC.
Control Signals from Control Bus: Signals from the system bus provide instructions to the control unit.
Output out of the Control Unit
Control signals within the processor: These are two types: those that cause data to be moved from one register to another, and those that activate specific
ALU functions.
Control signals to control bus: These are also of two types: control signals to memory, and control signals to the I/O modules
Functioning of a Microprogrammed Control unit
The control unit functions as follows:
1. To execute an instruction, the sequencing logic unit issues a READ command to the control memory.
2. The word whose address is specified in the control address register is read into the control buffer register.
3. The content of the control buffer register generates control signals and next address information for the sequencing logic unit.
4. The sequencing logic unit loads a new address into the control address register based on the next-address information from the control buffer register and the ALU flags.
All this happens during one clock pulse.
Depending on the value of the ALU flags and the control buffer register, one of three decisions is made:
* Get the next instruction: Add 1 to the control address register.
* Jump to a new routine based on a jump microinstruction: Load the address field of the control buffer register into the control address register.
* Jump to a machine instruction routine: Load the control address register based on the opcode in the IR.
Advantages and Disadvantages of a Microprogrammed Control Unit
Advantages of Microprogrammed Control Unit:
* Simplifies control unit design, making it cheaper and less error-prone.
* Requires simple decoders and sequencing logic, unlike complex logic in hardwired units.
* Dominant in CISC architectures due to ease of implementation.
Disadvantages of Microprogrammed Control Unit:
* Slower than a comparable hardwired control unit.
* Hardwired control is preferred in RISC processors due to simpler instruction formats.
Tasks Done By Microprogrammed
Control Unit
The two basic tasks performed by a microprogrammed control unit are as follows:
Microinstruction sequencing:
Based on the current microinstruction, condition flags, and the contents of the instruction register, a control memory address must be generated for the next microinstruction
Different techniques are based on the format of the address information in the microinstruction:
- Two Address Fields: Provides two possible next addresses based on condition flags.
- Single Address Field: One fixed address for the next microinstruction.
- Variable Format: Flexible address selection based on the control instruction format.
Microinstruction execution:
- Control Signal Generation: The control logic module generates control signals based on specific bits in the microinstruction.
- Purpose of Execution: Executing a microinstruction means generating control signals.
-
Signal Types:
Internal Control Signals: Control points within the processor.
External Control Signals: Signals sent to the control bus or other external interfaces.
Types of Microinstructions
Horizontal Microprogramming
Wide Memory Word: Uses a wide control word that contains multiple fields for control signals, allowing a large number of micro-operations to be specified at once.
High Degree of Parallel Operations: Since multiple bits control different micro-operations, it enables several operations to occur in parallel.
Little Encoding of Control Information: Control signals are explicitly defined, meaning minimal encoding is used. This reduces decoding complexity but increases memory space requirements.
Vertical Microprogramming
Narrow Memory Word: Has a narrow control word, so fewer bits are used compared to horizontal microprogramming, which reduces memory usage.
Limited Parallelism: Fewer control signals can be specified at once, leading to less parallelism.
Considerable Encoding: Control signals are encoded to save space, requiring additional decoding logic. This encoding often uses a small external memory word decoder to select the required control line.
RISC
Simplified Instruction Set:
Limited number of simple, fast-executing instructions.
Each instruction is of a fixed size, making them easy to decode.
Hardwired Control Unit:
Relies on a hardwired control unit for sequencing microinstructions, enabling faster processing.
On-Chip Cache Support:
Cache memory is integrated on the chip to improve performance by reducing memory access times.
Single-Chip Design:
All functional units are located on a single chip, which reduces size and increases speed.
Simple Pipelining:
Simplified instructions allow for easier implementation of pipelining, improving instruction throughput.
Large Set of CPU Registers:
RISC systems have many registers, reducing the need for memory access during instruction execution.
Few Addressing Modes:
Limited addressing modes, making instruction execution faster and simpler.
Easier Superscalar Processor Construction:
The simplicity of RISC makes it easier to build superscalar processors, allowing multiple instructions to be executed in parallel.
Examples:
IBM RS6000, MC88100, DEC Alpha series.
CISC
Extensive Instruction Set:
Instruction sets contain 120-350 instructions, which can perform complex tasks with fewer instructions.
Variable Instruction Format:
Instructions and data have variable formats, accommodating complex operations but increasing decoding complexity.
Small Set of Registers:
Typically 8-24 general-purpose registers, making the system more dependent on memory access.
Multiple Addressing Modes:
Numerous addressing modes allow for flexible data manipulation.
High Dependency on Microprogramming:
CISC architectures use microprogramming to simplify control unit design, although it may slow down execution.
Complex Instructions for High-Level Language Support:
Supports advanced features for high-level programming languages (HLL).
Complex Pipelining:
Due to complex instruction sets, CISC pipelining is challenging to implement.
Multi-Chip Design:
Often requires several chips to integrate all functional units, unlike RISC’s single-chip approach.
Difficult Superscalar Processor Design:
The complexity of CISC makes designing superscalar processors more challenging.
Examples:
Intel 386, 486, Pentium series, Motorola 68000 series.
Differentiate between RISC and CISC Architecture
RISC Features
Instruction Set: Small, fixed-size, and simple instructions.
Control Unit: Uses a hardwired control unit.
Pipelining: Simple to implement.
Registers: Has many registers, reducing memory access.
Addressing Modes: Limited number of addressing modes.
Superscalar Construction: Easier to design superscalar processors.
Chip Design: All functional units are on a single chip.
CISC Features
Instruction Set: Large, variable-size instructions with complex operations.
Control Unit: Uses a microprogrammed control unit.
Pipelining: Complex and challenging to implement.
Registers: Has fewer registers, leading to higher dependency on memory access.
Addressing Modes: Provides a wide variety of addressing modes.
Superscalar Construction: More difficult to design due to complexity.
Chip Design: Often requires multiple chips to accommodate all functions.
