Memory organization 1 - 5 Flashcards
- memory and memory units - memory hierarchy design and characteristics -byte and world addressable memory - simultaneous and hierarchical access memory organization - Register allocations in code generation
Memory devices are digital system that store data either temporarily or for a long term. Digital computers to hard disk have built in memory devices that can store data of user or manufacturers. The data either be in the form of control programs or programs that boot the system. Hence, to store such huge amount of data the memory devices must have enormous capacity. The challenge is to build memory devices that have large capacity but cost effective. The memory devices must be capable of storing both permanent data and instantaneous data.
Memories are made up of registers. Each register in the memory is one storage location. The storage location is also called a memory location. Memory locations are identified using Address. The total number of bits a memory can store is its capacity.
A storage element is called a Cell. Each register is made up of a storage element in which one bit of data is stored. The data in a memory are stored and retrieved by the process called writing and reading respectively.
word
a group of bits where a memory unit stores binary information. A word with a group of 8 bits is called a byte.
A memory unit consists of data lines, address selection lines, and control lines that specify the direction of transfer.
bit (binary units)
bit is a logical representation of the electric state. It can be 1 or 0.
nibble
it means the group of 4 bits.
byte
a byte is a group of 8 bits.
Kilobyte (kb): 1kb = 1024 byte
Megabyte (mb): 1mb = 1024 kb
Gigabyte (gb): 1gb = 1024 mb
Terabyte (tb): 1tb = 1024 gb
Petabyte (pb): 1pb = 1024 tb
Byte addressable memory
When the data space in the cell = 8 bits then the corresponding address space is called as Byte Address.
Based on this data storage i.e. Bytewise storage, the memory chip configuration is named as Byte Addressable Memory.
For eg. : 64K X 8 chip has 16 bit Address and cell size = 8 bits (1 Byte) which means that in this chip, data is stored byte by byte.
It is suitable for the processes that require data comprising single byte at a time. A single address is issued for accessing a single byte in byte addressable memory.
Byte addressable memory
When the data space in the cell = 8 bits then the corresponding address space is called as Byte Address.
Based on this data storage i.e. Bytewise storage, the memory chip configuration is named as Byte Addressable Memory.
For eg. : 64K X 8 chip has 16 bit Address and cell size = 8 bits (1 Byte) which means that in this chip, data is stored byte by byte.
It is suitable for the processes that require data comprising single byte at a time. A single address is issued for accessing a single byte in byte addressable memory.
Word addressable memory
When the data space in the cell = word length of CPU then the corresponding address space is called as Word Address.
Based on this data storage i.e. Wordwise storage, the memory chip configuration is named as Word Addressable Memory.
For eg. : For a 16-bit CPU, 64K X 16 chip has 16 bit Address & cell size = 16 bits (Word Length of CPU) which means that in this chip, data is stored word by word.
In case of word addressable memory, the necessary condition involves computing the address of word that contains required byte, fetch that word and then extraction of needed byte from the two byte word takes place. So, it is indirectly accessible. Hence, modern machines are byte addressable.
registers
fastest locations in the memory hierarchy. But unfortunately, this resource is limited. It comes under the most constrained resources of the target processor. Register allocation is an NP-complete problem. However, this problem can be reduced to graph coloring to achieve allocation and assignment. Therefore a good register allocator computes an effective approximate solution to a hard problem.
Allocation
Maps an unlimited namespace onto that register set of the target machine.
Reg. to Reg. Model: Maps virtual registers to physical registers but spills excess amount to memory.
Mem. to Mem. Model: Maps some subset of the memory location to a set of names that models the physical register set.
Allocation ensures that code will fit the target machine’s reg. set at each instruction.
Assignment
Maps an allocated name set to the physical register set of the target machine.
Assumes allocation has been done so that code will fit into the set of physical registers.
No more than ‘k’ values are designated into the registers, where ‘k’ is the no. of physical registers.
General register allocation is an NP-complete problem
Solved in polynomial time, when (no. of required registers) <= (no. of available physical registers).
An assignment can be produced in linear time using Interval-Graph Coloring.
Local register allocation and assignment
Allocation just inside a basic block is called Local Reg. Allocation. Two approaches for local reg. allocation: Top-down approach and bottom-up approach.
Top-Down Approach is a simple approach based on ‘Frequency Count’. Identify the values which should be kept in registers and which should be kept in memory.
Algorithm:
Compute a priority for each virtual register.
Sort the registers into priority order.
Assign registers in priority order.
Rewrite the code.
beyond single Blocks
More complicated because the control flow enters the picture.
Liveness and Live Ranges: Live ranges consist of a set of definitions and uses that are related to each other as they i.e. no single register can be common in a such couple of instruction/data.
Memory organisation:
Simultaneous Access Memory Organisation
In this organisation, CPU is directly connected to all the levels of Memory.
CPU accesses the data from all levels of Memory simultaneously.
For any “miss” encountered in L1 memory, CPU can directly access data from higher memory levels
(i.e. L2, L3, …..Ln).
If H1 and H2 are the Hit Ratios and T1 and T2 are the access time of L1 and L2 memory levels respectively then the
Average Memory Access Time can be calculated as:
T=(H1T1)+((1-H1)H2*T2
Memory organisation:
Hierarchical Access Memory Organisation
In this organisation, CPU is always directly connected to L1
i.e. Level-1 Memory only.
CPU always accesses the data from Level-1 Memory.
For any “miss” encountered in L1 memory, CPU cannot directly access data from higher memory levels(i.e. L2, L3, …..Ln). First the desired data will be transferred from higher memory levels to L1 memory.
Only then it can be accessed by the CPU.
If H1 and H2 are the Hit Ratios and T1 and T2 are the access time of L1 and L2 memory levels respectively then the
Average Memory Access Time can be calculated as:
T=(H1T1)+((1-H1)H2*(T1+T2)
Computer system design:
Memory hierarchy
an enhancement to organize the memory such that it can minimize the access time. The Memory Hierarchy was developed based on a program behavior known as locality of references.
Why Memory Hierarchy is Required in the System?
Memory Hierarchy is one of the most required things in Computer Memory as it helps in optimizing the memory available in the computer. There are multiple levels present in the memory, each one having a different size, different cost, etc. Some types of memory like cache, and main memory are faster as compared to other types of memory but they are having a little less size and are also costly whereas some memory has a little higher storage value, but they are a little slower. Accessing of data is not similar in all types of memory, some have faster access whereas some have slower access.
Memory hierarchy:
External Memory or Secondary Memory
Comprising of Magnetic Disk, Optical Disk, and Magnetic Tape i.e. peripheral storage devices which are accessible by the processor via an I/O Module.