memory

Question 1

types of memory

Answer 1

ROM
SRAM -static
DRAM -dynamic

Question 2

structure of memory

Answer 2

2 dimensional array of bits (latches) - each cell contains a single bit
N address bits, M data bits
2^N rows, M columns
array size 2^N x M. depth = rows = number of words
width = columns = size of words

Question 3

wordline

Answer 3

comes out of decoder, single row in memory array to be read/written. only one word (address) line to be high at a time
if wordline is high, stored bit should drive the bitline, otherwise leaves bitline floating

Question 4

how activating wordline works

Answer 4

MAR sends bits to decoder, bit on each line put together and translated- points to number of wordline. required wordline is active. stored bits drive the bitline value. the bitlines go to the MDR

Question 5

interface between CPU and memory

Answer 5

MAR: holds the ‘open’ address - CPU activates the groups of bytes required using the address line
MDR: holds the activated data
normal to address .8 bytes at a time but CPU can isolate individual bytes

Question 6

lines controlling a memory cell

Answer 6

wordline/address line: activates a set of bits driving the bitline
read/write line: determines whether data will be transferred to (write) or from the MDR (read)

Question 7

read from MDR takes place when?

Answer 7

bitlines are left floating at the MDR so take their values (weakly) from the active memory cells in the address line
R/W line = 1

Question 8

write from MDR takes place when?

Answer 8

bitlines strongly driven by MDR data + overpower the weakly held bits in the active memory cells, overwriting contents
R/W line = 0

Question 9

RAM

Answer 9

-named to distinguish from serial memory i.e. magnetic tape
DRAM: more dense but needs refreshing
SRAM: less dense but more stable
volatile, memory lost in power off

Question 10

ROM

Answer 10

-named bc originally read only
memory persists even when power removed
modern ROM can be written to e.g. flash/SSD

Question 11

DRAM consists of

Answer 11

• one transistor and capacitor for each bit

- capacitor charged or discharged to represent a bit

Question 12

how DRAM works

Answer 12

when address line activated, the capacitor is connected to the bit line. if bit line = floating, the bits set the bit line voltage weakly to high or low.
if bit line is driven, it overrides the capacitor and sets it to a new value

Question 13

adv DRAM

Answer 13

• structural simplicity: only one transistor/ capacitor needed for each bit = more dense vs 6 transistors for SRAM
• cheaper, less power required

Question 14

disadv DRAM

Answer 14

-reading and time causes bits to decay/capacitors to discharge. so reading/writing needs to be done every few (64ms) ms = refreshing memory = more circuitry, adding to cost

Question 15

SRAM consists of

Answer 15

6 transistors. uses bistable latching circuitry (flip flops) to store each bit as a voltage

Question 16

adv SRAM

Answer 16

high speed as uses 6 transistors for each memory cell + refreshing not necessary/more stable

Question 17

disadv SRAM

Answer 17

uses more power + more expensive + lower density

Question 18

basic ROM, how to read

Answer 18

the bit line is weakly set to high, and the address line is activated.
if cell contains 0: transistor connects bitline to ground, and bitline goes low
if cell contains 1: bitline retains weak high it was initialised with

Question 19

PROM- programmable ROM

Answer 19

all bit cells have a transistor. at a sufficient voltage, fuse of transistor can be blown, disconnecting transistor from ground, allowing memory cell to hold 0, instead of 1

Question 20

FLASH memory works how?

Answer 20

floating gate transistors can be activated or deactivated electrically

Question 21

multi-ported memory

Answer 21

memory that can access more than one address line at once

Question 22

multi-ported memory consists of

Answer 22

inputs AD1, AD2: address always used for read
AD3: address used for optional writing
WD3: data line for data to be written

outputs WD1, WD2: holds data read from AD1/AD2
WE1: write enable line. 0 = no write, 1 = write WD3 to A3
CLK

Question 23

how many different address locations can be decoded depends on

Answer 23

number of bits of MAR: k bits, number of memory locations = 2^k

Question 24

memory hierarchy

Answer 24

virtual memory -> main memory -> cache
largest -> smallest capacity
slowest -> fastest speed

Question 25

memory speed vs CPU speed

Answer 25

memory is slow compared to CPU speed. registers are faster (in CPU) whereas memory is on a separate chip

Question 26

how to overcome issues from memory speed

Answer 26

• wide path memory access: retrieve > 1 byte at a time
• memory interleaving: break down memory into subsections each with a MDR and MAR
• cache

Question 27

wide path memory access

Answer 27

• 8 bytes at a time, then CPU can separate + manipulate individual ones using extra circuitry
• wider data bus + MDR
• diminishing returns: widening path = more hardware, extra bytes less likely to be used often

Question 28

memory interleaving

Answer 28

break memory into chunks that can be accessed simultaneously
interleave so consecutive addresses can be accessed simultaneously
each chunk has its own MDR and MAR
useful for parallelisation/pipelining

Question 29

cache

Answer 29

preload with data you are likely to use e.g. data near addresses recently accessed
on CPU die so faster access
more expensive SRAM

Question 30

locality

Answer 30

temporal + spatial locality:
temporal- locality in time. if data recently used, likely to use it again soon so store up high in memory hierarchy to exploit
spatial- locality in space. if data recently used, likely to use nearby data soon so store up high in memory hierarchy to exploit

Question 31

cache hit and miss concept

Answer 31

CPU memory request goes to the cache controller, which checks request against each tag in cache. if theres a hit- cache location is used instead of memory.
if there is a miss- cache controller selects a line for replacement from memory. then new line in cache is treated as before

Question 32

multi level cache

Answer 32

as levels increase, cache gets larger but further away = slower. still better than main memory

Question 33

hit ratio

Answer 33

ratio of hits to total requests: 90% most common but 50%+ improves execution speed

Question 34

why caching works

Answer 34

locality of reference: most memory references confined to a small region of memory at any time e.g. arrays/loops/variables stored together

Question 35

synchronising cache and memory

Answer 35

write through: when data is written to cache, it is immediately written to memory
write back: when data is written to cache, it is only written to memory when the cache block is flushed