memory Flashcards
types of memory
ROM
SRAM -static
DRAM -dynamic
structure of memory
2 dimensional array of bits (latches) - each cell contains a single bit
N address bits, M data bits
2^N rows, M columns
array size 2^N x M. depth = rows = number of words
width = columns = size of words
wordline
comes out of decoder, single row in memory array to be read/written. only one word (address) line to be high at a time
if wordline is high, stored bit should drive the bitline, otherwise leaves bitline floating
how activating wordline works
MAR sends bits to decoder, bit on each line put together and translated- points to number of wordline. required wordline is active. stored bits drive the bitline value. the bitlines go to the MDR
interface between CPU and memory
MAR: holds the ‘open’ address - CPU activates the groups of bytes required using the address line
MDR: holds the activated data
normal to address .8 bytes at a time but CPU can isolate individual bytes
lines controlling a memory cell
wordline/address line: activates a set of bits driving the bitline
read/write line: determines whether data will be transferred to (write) or from the MDR (read)
read from MDR takes place when?
bitlines are left floating at the MDR so take their values (weakly) from the active memory cells in the address line
R/W line = 1
write from MDR takes place when?
bitlines strongly driven by MDR data + overpower the weakly held bits in the active memory cells, overwriting contents
R/W line = 0
RAM
-named to distinguish from serial memory i.e. magnetic tape
DRAM: more dense but needs refreshing
SRAM: less dense but more stable
volatile, memory lost in power off
ROM
-named bc originally read only
memory persists even when power removed
modern ROM can be written to e.g. flash/SSD
DRAM consists of
- one transistor and capacitor for each bit
- capacitor charged or discharged to represent a bit
how DRAM works
when address line activated, the capacitor is connected to the bit line. if bit line = floating, the bits set the bit line voltage weakly to high or low.
if bit line is driven, it overrides the capacitor and sets it to a new value
adv DRAM
- structural simplicity: only one transistor/ capacitor needed for each bit = more dense vs 6 transistors for SRAM
- cheaper, less power required
disadv DRAM
-reading and time causes bits to decay/capacitors to discharge. so reading/writing needs to be done every few (64ms) ms = refreshing memory = more circuitry, adding to cost
SRAM consists of
6 transistors. uses bistable latching circuitry (flip flops) to store each bit as a voltage
adv SRAM
high speed as uses 6 transistors for each memory cell + refreshing not necessary/more stable
disadv SRAM
uses more power + more expensive + lower density
basic ROM, how to read
the bit line is weakly set to high, and the address line is activated.
if cell contains 0: transistor connects bitline to ground, and bitline goes low
if cell contains 1: bitline retains weak high it was initialised with
PROM- programmable ROM
all bit cells have a transistor. at a sufficient voltage, fuse of transistor can be blown, disconnecting transistor from ground, allowing memory cell to hold 0, instead of 1
FLASH memory works how?
floating gate transistors can be activated or deactivated electrically
multi-ported memory
memory that can access more than one address line at once
multi-ported memory consists of
inputs AD1, AD2: address always used for read
AD3: address used for optional writing
WD3: data line for data to be written
outputs WD1, WD2: holds data read from AD1/AD2
WE1: write enable line. 0 = no write, 1 = write WD3 to A3
CLK
how many different address locations can be decoded depends on
number of bits of MAR: k bits, number of memory locations = 2^k
memory hierarchy
virtual memory -> main memory -> cache
largest -> smallest capacity
slowest -> fastest speed
memory speed vs CPU speed
memory is slow compared to CPU speed. registers are faster (in CPU) whereas memory is on a separate chip
how to overcome issues from memory speed
- wide path memory access: retrieve > 1 byte at a time
- memory interleaving: break down memory into subsections each with a MDR and MAR
- cache
wide path memory access
- 8 bytes at a time, then CPU can separate + manipulate individual ones using extra circuitry
- wider data bus + MDR
- diminishing returns: widening path = more hardware, extra bytes less likely to be used often
memory interleaving
break memory into chunks that can be accessed simultaneously
interleave so consecutive addresses can be accessed simultaneously
each chunk has its own MDR and MAR
useful for parallelisation/pipelining
cache
preload with data you are likely to use e.g. data near addresses recently accessed
on CPU die so faster access
more expensive SRAM
locality
temporal + spatial locality:
temporal- locality in time. if data recently used, likely to use it again soon so store up high in memory hierarchy to exploit
spatial- locality in space. if data recently used, likely to use nearby data soon so store up high in memory hierarchy to exploit
cache hit and miss concept
CPU memory request goes to the cache controller, which checks request against each tag in cache. if theres a hit- cache location is used instead of memory.
if there is a miss- cache controller selects a line for replacement from memory. then new line in cache is treated as before
multi level cache
as levels increase, cache gets larger but further away = slower. still better than main memory
hit ratio
ratio of hits to total requests: 90% most common but 50%+ improves execution speed
why caching works
locality of reference: most memory references confined to a small region of memory at any time e.g. arrays/loops/variables stored together
synchronising cache and memory
write through: when data is written to cache, it is immediately written to memory
write back: when data is written to cache, it is only written to memory when the cache block is flushed
