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Computer Systems > computer architecture pt2 > Flashcards

computer architecture pt2 Flashcards

1
Q

FDE cycle

A

CPU sends value of PC to be copied to MAR
PC increments
get instruction identified by MAR and copy into MDR
move instruction from MDR to IR
move instruction from IR to CU for decoding:
-sends operation to ALU
-put address of data to be operated on in a register
-send address of data from register to MAR
-read data and place in MDR
-move data from MDR to an accumulator in the ALU
-complete operation and store result in an accumulator in the ALU

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2
Q

uses of alternative addressing modes

A
  • addressing large amount of memory with few bits
  • use indexes to loop or examine a table or array
  • address registers (bc faster than addressing memory)
  • relocate data or programs in memory
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3
Q

direct addressing

A

the address used is the address holding the data to be operated on

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4
Q

immediate addressing

A

the address read in the instruction is the data to be used (e.g. for constants like 1)

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5
Q

indirect addressing *

A

the address used is the address of the memory location holding the address of the data item to be operated on

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6
Q

register indirect addressing

A

the address read in the instruction is the address of the register holding the data item to be operated on

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7
Q

indexed addressing @

A

the address in the instruction has an index (stored in a register) which is added to obtain the address of the data

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8
Q

impure code

A

when instructions are changed during execution

changed instructions have to be reset before being run again else program will run differently

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9
Q

full instruction structure

A

opcode + addressing mode + address 1 + address 2

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10
Q

absolute addressing

A

the address read is the address that should be gone to

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11
Q

relative addressing

A

the address read in the instruction is an offset to the current instruction address (i.e. program counter value)

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12
Q

base offset addressing

A

the address read in the instruction is offset by the current value in a special base register

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13
Q

type of instructions

A

Single operand manipulation: negating, inc/decrementing, setting reg = 0
Arithmetic: floating point, add/sub/div/multiplication
Program control: branching, call, jumps, return
Boolean logic: shift/rotate, bit manipulation- allowing the design of own flags so controlling program flow. inc set/test instructions
Data movement: between registers, reg+memory + memory locations
Stack: pop/push in a LIFO structure
Multiple data, single instruction: multimedia- single instruction on a large amount of date e.g. pixels

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14
Q

MIPS principles

A
  1. simplicity favours regularity
  2. makes the common case faster
  3. smaller is faster
  4. good design demands good compromises
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15
Q

1.simplicity favours regularity

A

consistent instruction format with same number of operands- 2 sources + 1 destination- : easier to encode + handle in hardware

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16
Q
  1. makes common case faster
A

only includes simple, commonly used instructions
for complex operations, use more instructions
results in simpler, smaller, faster hardware
(RISC)

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17
Q
  1. smaller is faster
A

few registers used

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18
Q
  1. good design demands good compromises
A

more instruction formats = more flexibility
number of instruction formats kept small to adhere to principle 1 + 3
other formats may appear in assembler but transformed in machine code to fit format

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19
Q

3 instruction formats

A
  • R type: register operands
  • I type: immediate operand
  • J type: jumping
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20
Q

r-type instruction formats

A

opcode (6 bits, 0 for r-type), rs, rt (source registers, 5 bits), rd (destination register, 5 bits), shamt (shift amount, 5 bits, 0 if not shift operation), func (function, operation to be done, 6 bits)

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21
Q

register field values: shift bits in register 17 left 5 places and put in in register 16

A 
opcode = 0
rs = 0
rt = 17
rd = 16
shamt = 5
func = 0
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22
Q

i-type instruction formats

A

opcode (6 bits), rs, rt (source registers, 5 bits), imm (16 bit twos complement immediate)
rt is used as a destination for some instructions e.g. addi

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23
Q

addi $s0, $s1, 5

A

(immediate type) add the value in register 17, and the number 5, and place in register 16

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24
Q

lw $t2, 32($0)

A

load word at address 32+ contents of register 0, and store in register 10

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25
Q

sw $s1, 4($t1)

A

store word in register 17 at address 4+ contents of register 9

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26
Q

li $s0, 5

aka ori $s0, $0, 5

A

(immediate type) load immediate 5 and store in register 16

in machine code, swap round $0 and $s0

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27
Q

j-type

A

6 bit opcode, 26 bit address

typically use r type rather than this in assembler: jr name/ jr $0 i.e. jump to name or address contained in register

28
Q

types of addressing the operands

A

register only: add $s0, $s1, $s2
immediate: addi $s0, $s1, 5 (5+ contents of s1, store in s0: s1 = rs, s0 = rt)
base address: address of operand = base address + signed immediate e.g. lw $1, 0($2)
PC-relative (jump so far from current position): beq $t0, $0, 3 (offset of 3 from PC value if first two values are equal)

29
Q

loading 32 bit words with only 16 bit intermediates

A

first load first half then add on the second half
lui $0, 0xFEDC
ori $s0, $s0, 0x8765

30
Q

how to make OS calls

A

use register $v0, system call depends on contents of $v0. assembly code ‘syscall’

31
Q

multiplication MIPS

A

mul: 32 bit result, no overflow checking
mult: 32 bits multiplied resulting in 64 bit result (mult $s0, $s1) stored in special reg: lo/hi
turn mult in to mul $v2,$s3,$t0 by mflo $v2

32
Q

division MIPS

A

div $s0, $s1
quotient in lo
remainder in hi

33
Q

move from lo/hi special registers

A

mflo $s2

mfhi $s2

34
Q

MIPS: jal instructions

A

jump and link:
e.g. jal adder, jumps to portion labeled “adder:”, and puts return address (current address) in $ra
return back justing jr $ra

35
Q

caller vs callee

A

caller: passes arguments to callee using $a0 - $a4 and jumps to callee using jal
callee: performs function + returns result using $v0-$v1, returns to point of call using jr $ra, shouldnt overwrite registers needed by caller e.g. $s0-$s7, $ra, $sp- if using the registers, values kept on stack

36
Q

stack

A

dynamically sized chunk of memory with $sp containing address of head of stack

37
Q

pushing to stack

A

move stack pointer down one position and write value
addi $sp, $sp, -4
sw $s0, 0($sp)

38
Q

popping from stack

A

read and move pointer back up four places
addi $sp, $sp, 4
lw $s0, 0($sp)

39
Q

$ra when calling recursive procedures

A

push value of $ra onto stack before calling a function so can reinstate afterwards

40
Q

conventional orders of caller

A
  • arguments in $a0-$a3
  • save any needed registers: $ra, maybe $t0-$t9
  • jal callee
  • restore registers
  • check $v0 for result
41
Q

conventional orders of callee

A
  • save registers that may be disturbed $s0-$s7
  • perform function
  • result in $v0
  • restore registers
  • jr $ra
42
Q

architecture

A

consists of the instruction set + implies an architectural state:

  • value of PC
  • state of all architecture defined registers
43
Q

microarchitecture

A

how to implement an architecture in hardware. consists of:

  • datapath: functional blocks and registers
  • control: control signals
44
Q

MIPS

A
  • approx 80 instructions
  • 32 general purpose instructions $0- $31
  • super pipelined: each instruction is broken down into a sequence of ‘micro’ instructions
  • RISC
  • $0 is special and always contains 0
45
Q

program counter

A

32 bit register: PC’ = input = address of next instruction, output PC = points to current instruction

46
Q

instruction memory

A

one read port

read port: 1 read address, A, of 32 bit length, reads 32 bit data (instruction) and place on RD

47
Q

register file

A

one read port one write port.
read port: 2 input addresses of 5 bits (addressing one of 32 registers). addresses read from these are placed on RD1 and RD2 outputs
write port: CLK, WD- 32 bit data to be written, A3 5 bit destination address, WE- write enable: if 1 then written to specified register on a rising edge of clock

48
Q

data memory

A

one read port one write port
read port: 32 bit address, A
write port: 32 bit write data, WD
WE: write enable, if 1 WD written into address A on rising edge else data read from A and placed on RD output (32 bit)

49
Q

all reads in MIPS state elements are ‘combinational’

A

change in address results in change in read data (after a delay). writes are only on a rising clock edge

50
Q

further registers

A

32 in ‘floating point unit’: each hold a single precision floating point value. pairs store double precision numbers
mul.s $f0, $f1, $f2 multiply f2 and f1 and store in f0
mul.d operands are doubles stored in
$f2,$f3 and $f4,$f5, result is stored in $f0 and $f1.
also exception and interrupt handling registers

51
Q

mtc1 $s0, $f0

mfc1 $f0, $s0

A

move between CPU and FPU
move to coprocessor 1
move from coprocessor 1

52
Q

lwc1 $f0, 4($s0)

swc1 $f0, 4($s0)

A

load word save word

memory address is in CPU

53
Q

l. d $f0, 4($s0)

s. d $f0, 4($s0)

A

load double and save double precision numbers

54
Q

casting:

cvt.s.w $f0,$f0

A

converts from int (w) to single FP

55
Q

Single precision (32-bit) floating point numbers have

A

1 sign bit
8 bit exponent
23 bit mantissa

56
Q

casting errors

A

if number needs more digits for mantissa and only 23 provided

57
Q

floating point branches: Logical comparisons

A 
equality: c.eq.s, c.eq.d
Less than: c.lt.s, c.lt.d 
Less than or equal: c.le.s, c.le.d 
(ge = greater than or equal)
result of logical comparison stored in fpcond
58
Q

fp branches: conditional branch

A

bclf: branches if fpcond is FALSE
bclt: branches if fpcond is TRUE

59
Q

MMIO

A

memory mapped input output: devices connected to same address bus as main memory and are each allocated address space (input devices read like any other memory, output devices written to like any other memory). CPU doesn’t see difference between IO and memory

60
Q

port-mapped IO

A

have a separate address space for IO and use special IO instructions to access IO

61
Q

MARS: keyboard allocated 2 memory addresses

A

0xffff0000 control: bit 0 = ready bit, 1 if unread input from keyboard
bit 1 = interrupt bit, if 1 then keyboard triggers an interrupt
0xffff0004 data: contains the ASCII code of the last key pressed. on read it triggers the ready bit to be reset

62
Q

MARS: display output

A

0xffff0008 control: bit 0 = ready bit, 1 if display is ready to take another input
bit 1 = interrupt bit, if 1 then display ready triggers an interrupt
0xffff000c data: set with the ASCII code of the character
on write: triggers the ready bit to be reset

63
Q

exception

A

anything that happens that triggers an unscheduled function call in the middle of a user program. caused by hardware = interrupt, software = traps e.g. undefined function

64
Q

when an exception occurs

A

program records cause of exception, jumps to exception handler and returns to program

65
Q

special addresses used when exception occurs

A

EPC: stores value of program counter
status: records whether user or kernel code was being executed
cause: records cause of exception
BadVaddress: stores the bad address that caused an exception
-these are stored in coprocessor 0
mfc0 $t0 EPC- moves contents of EPC to t0

66
Q

flow during exception

A

processor stores cause and exception PC in cause and EPC
processor jumps to exception handler
exception handler:
saves register on stack
reads cause from cause register mfc0 $t0, Cause
handles exception
restores registers
returns to program
mfc0 $k0, EPC
jr $k0
-must save all registers so registers can be reinstated and program run as if nothing had happened

Computer Systems (6 decks)

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