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Computer Systems > LMC > Flashcards

LMC Flashcards

1
Q

components of LMC

A
  • mailboxes: 3 digits –> 100 is max
  • counter: 2 buttons- 1 increments and other resets to 00
  • calculator: 3 digits: 0-9, +, - buttons, flag for -ve results
  • input/output trays: input by user, output sent to user
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2
Q

routine in LMC

A
  • looks at counter for mailbox number
  • increments counter by 1
  • goes to mailbox + reads 3 digits
  • completes action indicated by digits
  • restarts…
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3
Q

how do instructions work

A

3 digits: first is opcode (instructions), last digits are operand (mailbox number)

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4
Q

opcode 1

A

add: go to specified mailbox, read 3 dig number at address, go to calculator and add number to that on calculator

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5
Q

opcode 2

A

subtract: go to specified mailbox, read 3 dig number at address, go to calculator and subtract number from that on calculator

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6
Q

opcode 3

A

store: go to calculator, read 3 dig value, go to specified mailbox and store value there (overriding currently stored value)

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7
Q

opcode 5

A

load: go to mailbox specified in instruction, read in the 3 dig number, and enter into calculator (overriding current value)

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8
Q

opcode 6

A

branch: set program counter to the 2 address specified in instruction, and start fetch of instruction

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9
Q

opcode 7

A

branch on zero: check calculator, if value = 0, set program counter to address specified in instruction and start fetch else continue with next instruction as normal

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10
Q

opcode 8

A

branch on positive: check calculator, if +ve (inc 0), set program counter to address specified in instruction and start fetch else continue with next instruction as normal

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11
Q

instruction 901

A

input: go to IN tray, read 3 dig number there, go to calculator and enter value there. only read one input slip, then remove it, any others are used for future visits

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12
Q

instruction 902

A

output: go to calculator, read 3 digit value there and leave slip with value on OUT tray

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13
Q

opcode 0

A

break

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14
Q

fetch

A

find the instruction to execute: reads program counter, goes to mailbox at that address in instruction, reads 3 dig value

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15
Q

execute e.g. store

A

target address remembered. 3 digits in calculator read, 3 digits written in mailbox at target address. program counter incremented

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16
Q

von neumann

A
  • same memory for instructions and data
  • memory is addressed linearly: there is a number for every mailbox
  • memory addressed by location: contents is irrelevant
  • instructions executed sequentially unless branch or reset
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17
Q

harvard

A

-separate memory for instructions and data:
-avoids potential for malware and bugs from self-modifying code
-simpler to read and analyse code
-quicker to execute as can access instructions and data simultaneously
modern processors have split cache so best of harvard and VN

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18
Q

five major components of a CPU

A
  • memory (RAM)
  • registers
  • ALU
  • control unit
  • buses
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19
Q

memory (RAM)

A

mailboxes

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20
Q

registers

A

special memory locations that can be accessed very fast and are manipulated directly by the CU 1-128 bits: includes program counter (PC), instruction register (IR), accumulator
have a defined purpose and wired to perform that purpose
holds binary values temporarily for storage, manipulation, calculations

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21
Q

ALU

A

calculator

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22
Q

buses

A

bundles of tiny wires- electrical conductors i.e. lines carrying signals- that carry data between components: address, data, control, power

  • -carries data between different points on CPU
  • carries data between CPU and main memory/computer peripherals*
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23
Q

control unit

A

responsible for directing flow of data and instructions within the CPU- compromised of multiplexor and decoder

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24
Q

accumulator

A

register part of the ALU. holds data + interim and final results of calculations + data to be transferred between different memory locations + (I/O+memory)

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25
Q

registers int the CU

A

PC, IR, flags

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26
Q

PC

A

holds the address of the next instruction to be executed

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27
Q

IR

A

holds the instruction currently being executed

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28
Q

flags

A

1 bit memory to keep track of special conditions- grouped together in 1+ status registers
e.g. arithmetic carry, power failure, internal computer error, overflow

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29
Q

memory address register

A

holds address of the memory location to which data is to be written to
only written to

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30
Q

memory data register

A

holds value that is being stored to or retrieved from a memory location addressed by MAR
written to and from

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31
Q

types of bus

A

point to point- carries signal between specific source and specific destination
broadcast- carries signals to many different devices
bus interface bridges- allows communication between buses e.g. peripheral control interface bus, external bus, universal serial bus

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32
Q

translate cab.bc (subscript 3)

A

from units left then from radix right:
13^0 + 0 3^1 + 2* 3^2
+ 13^-1 + 23^-2
(a = 0, b = 1, c = 2)

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33
Q

group of

4 bits, 8 bits, 16 bits, 32 bits, 64 bits

A 
4 = nibble
8 = byte
16 = half word
32 = word
64 = double word
size of word = CPU dependent, some have 32/64 bit words
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34
Q

why hexadecimal

A
  • more compact
  • easier to read and write than binary
  • easy to convert between binary and hex
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35
Q

converting dec to binary

A 
repeatedly div by 2 until 0 or 2 is reached, the remainder is the binary digit (from radix point left)
e.g. 13(10) to binary:
13 div 2 = 6 rem 1
6 div 2 = 3 rem 0
3 div 2 = 1 rem 1
1 div 2 = 0 rem 1
therefore answer is 1101
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36
Q

converting dec fraction to binary

A 
repeatedly multiply fractional part by 2 until fractional part = 0, if result >= 1 then binary digit = 1. (from radix point right)
e.g. 0.8125(10) to binary:
0.8125 * 2  = 1.625 (1)
0.625 * 2 = 1.25 (1)
0.25 *2 = 0.5 (0)
0.5 * 2 = 1 (1)
therefore = 0.1101(2)
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37
Q

overflow error

A

when a computer attempts to handle a value too large for it. triggers the status register, but can cause errors.

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38
Q

binary multiplication

A
  • just like long multiplication for decimal numbers

- efficiently achieved using left shifts and add operations

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39
Q

negative representation of numbers

A

sign and magnitude, ones complement, twos complement, adding a bias

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40
Q

sign and magnitude

A

left most bit is a flag bit, 1 = -ve, 0 = +ve
two representations for 0: 0000 0000, 1000 0000
binary arithmetic is messy

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41
Q

ones complement

A

flip all bits, left most bit is still a flag bit
two representations for 0: 0000 0000, 1111 1111
binary addition is a bit simpler

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42
Q

twos complement

A

flip all bits and add 1, left most bit is still a flag bit
one representation for 0 (1111 1111 = -1)
binary arithmetic is much simpler

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43
Q

adding a bias (negative binary representation)

A

add a bias of ((2^k-1) -1) then store in normal binary.
allows storage of numbers -((2^k-1) -1) –> (2^k-1)
higher order bit does not indicate sign
used for floating point storage

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44
Q

negative subtraction

A

twos complement the second number and add

overflow is ignored

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45
Q

floating point representation

A

sign bit + exponent + mantissa

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46
Q

exponent

A

a number between -126 and 127, stored with a bias + 127 so number stored is between 0 and 255

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47
Q

0 and 255 special meanings

A

0 exponent + 0 mantissa = 0
0 exponent + non 0 mantissa = subnormal numbers
255 exponent + 0 mantissa = +/- infinity
255 exponent + non 0 mantissa = not a number

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48
Q

mantissa

A

e.g. 1.01…. binary number scaled so that leading 1 preceding radix point, don’t store leading 1 (assume its there)
store only the 23 digits of the fractional part

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49
Q

e.g. translate 0 sign bit + 124 exponent + 1.25 mantissa

A

0 = +ve
124 - 127 = -3 exponent
1.25 mantissa
therefore overall = 1.25*2^-3 = 1.25/8 =0.15625

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50
Q

translate -12.375 to floating point representation

A

1100.011 (2)
for leading 1: 1.100011 * 2^3
mantissa: 100011000…
exponent: 3+127 = 130 (10) = 1000 0010

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51
Q

floating point issues.

A

rounding error- cannot represent all numbers e.g. 0.1

have to limit to certain number of binary digits

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52
Q

floating point operations result in…

A

FP number closest to the answer

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53
Q

underflow/overflow level

A

underflow level = 2^-126 (-126 = smallest number that can be represented by exponent)
overflow level = (2-2^-23) * 2^127 (23 = number of digits of mantissa)

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54
Q

ariane 5 issue and how to overcome

A

overflow error, could not convert 64 bit FP to 16 bit signed integer
overcome by check if number outside range before conversion: if too large then set at a max value

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55
Q

transistor

A

electrically controlled switch: two ports (drain and source) are connected depending on voltage of a 3rd port (gate)

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56
Q

nMOS transistor

A

when g = 0, switch is OFF d is not connected to s
g = 1, switch is ON, d is connected to s
(see image L5)

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57
Q

pMOS transistor

A

when g = 0, switch is ON, s is connected to d
g = 1, switch is OFF, s is not connected to d
(see image L5)

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58
Q

most common transistor

A

MOSFET: metal oxide semiconductor field effect transistor

element used is silicon

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59
Q

most common element used in MOSFET and why

A

silicon: semiconductor since conductivity changes over many orders of magnitude depending on small changes in levels of dopants
- poor conductor of electricity since all 4 outer electrons involved in bonding

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60
Q

dopants

A

impurities providing extra electrons or electron holes increasing conductivity

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61
Q

n-type silicon

A

overall negative charge, the dopant added is Arsenic, it has an extra electron not involved in bonding which can carry charge

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62
Q

p-type silicon

A

overall positive charge, the dopant added is boron- it is short an electron so leaves a positive electron hole which can move around the lattice

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63
Q

diode

A

at a junction between p-type and n-type silicon, current can only flow from p-type to n-type

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64
Q

what happens at a junction of n-type and p-type silicon

A

electrons in the n-type region and electron holes in the p-type region cancel each other out, creating a ‘depletion region’
there are no mobile charge carriers in this region

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65
Q

how is binary addition implemented

A

using gates implementing boolean algebra

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66
Q

AND algebraic expression

A

Y = A . B (dot in centre)

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67
Q

OR algebraic expression

A

Y = A + B

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68
Q

NOT algebraic expression

A

Y = A- (line above A)

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69
Q

p-type and n-type junction:

positive voltage applied to p and negative voltage applied to n

A

electron holes in p-type attracted towards n-type
electrons in n-type attracted towards p-type
depletion region squeezed out and current flows

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70
Q

p-type and n-type junction:

negative voltage applied to p and positive voltage applied to n

A

electron holes in p-type repelled by the n-type and electrons in the n-type repelled by the p-type
depletion region expands and creates a barrier to current flow

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71
Q

issue at p -type and n-type junction trends

A

trends break down at sufficient voltage

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72
Q

capacitor

A

two pieces of conductive metal separated by an insulator.
if a positive voltage is applied to one side, it accumulates charge Q, and the other side the opposite charge -Q (not Q)
takes time and energy to charge/discharge a capacitor

73
Q

nMOS transistor, when gate g is at V(DD)

A

capacitor effect draws electrons to the surface, and they create a temporary channel of n-type silicon, so current can then flow from source to drain

74
Q

how to indicate 1s and 0s

A

high voltage = 1
low voltage = 0
voltages typically between 0V–> 5V with 0V = 0, 5V = 1, need to be able to tolerate noise though

75
Q

V(DD)

A
  • the high voltage, historically 5V

- modern chips with smaller transistors have lower max voltages e.g.3.3V to save power and avoid overloading transistors

76
Q

logic levels

A

defined to allow the mapping of continuous voltage to discrete 0 and 1 of the digital abstraction

77
Q

noise margin high and low calculations

A 
NM(H) = V(OH) - V(IH)
NM(L) = V(IL) - V(OL)
78
Q

the ideal inverter

A

the ideal inverter would output V(DD) for inputs up to V(DD)/2 and 0 above this

79
Q

reasonable choice of logic levels

A

on graph of V(A) vs V(Y), reasonable choice of logic levels are where slope = -1

80
Q

static discipline

A

design restriction that you only allow circuit elements that all satisfy the same logic levels: means you can successfully apply digital abstraction and combine elements without concern about logic levels or analogue values

81
Q

disadv of static discipline

A

reduces freedom to include arbitrary elements (but makes design simpler)

82
Q

moores law

A

transistor density doubles every two years

83
Q

graphical ways of representing boolean algebra

A
  • linear truth table
  • rectangular/coordinate table
  • venn diagram
84
Q

how many boolean operations on k inputs

A

2^2^k

85
Q

why is NAND used as a universal gate

A

easier to make

86
Q

NAND vs NOR, pMOS-wise

A

in NAND, the two pMOS are parallel and in NOR, the two pMOS are in series so NOR results in delays because of low mobility of holes

87
Q

pMOS vs nMOS speed of operations

A

nMOS is faster.

for pMOS to match this- size has to increase = more silicon = more expensive

88
Q

what are digital design principles about

A

about managing complexity of huge numbers of interacting elements

89
Q

list the digital design principles

A
  • abstraction: hiding irrelevant details
  • discipline: restricting design choices to make things easier to model, design+combine
  • hierarchy: breaking into modules+submodules
  • modularity: well-defined functions+interfaces for modules
  • regularity: encouraging uniformity so can reuse+swap modules
90
Q

circuit properties

A
  • 1+ discrete valued input terminals
  • 1+ discrete valued output terminals
  • specification of relationship between input+output
  • specification of delay between input received and output responding
91
Q

circuit is made up of

A

elements- circuit with inputs, outputs and specs

node-wire joining elements whose voltage conveys a discrete valued variable

92
Q

why combinational + sequential logic

A

-arbitrary circuits lead to short circuits and instability

93
Q

combinational logic rules

A
  • individual gates are combinational circuits
  • every circuit element must be a combinational circuit
  • every node is either an input to the circuit or connected to exactly one output of a circuit element
  • the circuit has no cyclic paths, every path through the circuit visits any node at most once
94
Q

boolean algebra

A

algebra of 1/0 variables used to specify function of a combinational circuit
used to analyse and simplify circuits required to give a specified truth table

95
Q

literals
AND of several literals are called…
OR of several literals are called…

A
  • variables or their complements
  • product/implicant
  • sum/implicant
96
Q

minterm

A

product involving all the inputs to a function

97
Q

maxterm

A

sum involving all the inputs to a function

98
Q

sum of products

A

every boolean expression can be written as minterms ORed together

99
Q

product of sums

A

every boolean expression can be written as maxterms ANDed together

100
Q

truth table to SOP

A

OR together the products of the literals that result in 1s

101
Q

truth table to POS

A

AND the 0 values of the function, negating any literals which = 1, so each literal = 0

102
Q

axioms dual

A

achieved by interchanging 1,0 and AND/OR

103
Q

axiom: binary field
axiom: NOT

A

B = 1 if B!=0; B=0 if B!= 1;

not 1 = 0; not 0 = 1

104
Q

AND/NOT

A

0 . 0 = 0, 1 . 1 = 1
0 + 0 = 0, 1 + 1 = 1
0 + 1 = 1, 0 . 1 = 0

105
Q

identity theorem

null theorem

A

B . 1 = B; B + 0 = B;

B + 1 = 1; B . 0 = 0;

106
Q

idempotency theorem
involution theorem
complements theorem

A

B+B = B; B . B = B
not not B = B
B + not B = 1; B . not B = 0

107
Q

prove B . 0 = 0

A

case B = 0:
0 . 0 = 0 (axiom)
case B = 1:
1 . 0 = 0 (axiom)

108
Q

commutativity
associativity
distributivity

A
  • swapping variables around
  • moving brackets around
  • distribution AND into an OR bracket or two OR brackets amongst each other
109
Q

covering
combining
consensus
de morgans

A

B . (B + C) = B; B + (B . C ) =B;
(B . C) + (B . notC) = B; (B+C) . (B+ notC) = B
(B + C) . (notB + D) . (C + D) = (B + C) . (notB + D) (+ v.v. with + and . switched)
(already know de morgans)

110
Q

why simplify boolean logic

A

represent the same thing with much less hardware

111
Q

each cell in a karnaugh map represents…

A

a minterm

112
Q

prime implicants

A

implicants that cant be combined with each other

113
Q

7 segment display driver

A

4 inputs D(3:0), 7 outputs.
the inputs represent a decimal digit 0-9
each output is a segment.
create a circuit for each segment determining whether segment should be lit up based on 4 inputs
unspecified inputs (for numbers>9) can be represented as 1/0 depending on what reduces circuitry

114
Q

difference between sequential and combinational circuit

A

combinational: output depends on input
sequential: output depends on state and input i.e. history of input

115
Q

e.g. of combinational circuits

A

adders: adds contents of two registers
multiplexors: uses a binary digit to select an input
decoders: uses a binary digit to activate a single line

116
Q

e.g. of sequential circuits

A

latches/flip-flops: basic memory element

117
Q

decoder

A

N inputs, 2^N outputs. only one of the outputs is 1 at a time, the rest are 0. which output is activated depends on the input

118
Q

larger decoders require

A

multi input AND gates requiring a lot of circuitry. instead can use deeper circuitry = less transistors but slower response time

119
Q

multiplexor

A

has k selector inputs and 2^k data inputs. the selector represents a binary number, indexing the data to be outputted

120
Q

how can 2:1 multiplexer be built

A
  • using sum of products logic

- using tristate buffers: tristate enables are arranged so that at all times, exactly one tristate buffer is active

121
Q

how can a 4:1 multiplexer be implemented

A

-out of smaller 2:1 multiplexers

122
Q

why cant you use a single transistor instead of a tristate buffer

A

the output of a single transistor isn’t driven

123
Q

inverting tristate: purpose of final pair of transistors

A

control transmission- aiding voltage drain

124
Q

propogation delay

A

max delay before the output is stable

125
Q

contamination delay

A

min time before output changes

126
Q

delay is caused by

A
  • resistance and capacitance in a circuit

- speed of light limitation

127
Q

why may t(pd) and t(cd) be different

A
  • different raising and falling delays
  • circuit may have multiple inputs and outputs, some of which are faster than others
  • circuits slow down when hot and speed up when cold
128
Q

critical path

A

longest path in a circuit, determining the propogation delay

129
Q

short path

A

shortest path in a circuit, determining the contamination delay

130
Q

glitch

A

output temporarily moving to an incorrect value before stabilising

131
Q

tristate delays

A

different characteristics for selector and data change with different delays for each

132
Q

gate delays in a full adder

A

3 gate delays, unless the first set of gates are pre-computed, in which case 2 gate delays once the C(in) comes in

133
Q

ripple adder

A

computation of the carry bit ripples through the chained adders

134
Q

how many gate delays for a k-bit ripple adder

A

3 + 2(k-1) = 2k + 1

135
Q

two functions used in a carry look ahead adder

A

G(A,B) = generate function = A AND B

P(A, B) = propagation function = A OR B

136
Q

Cout in a carry look ahead adder

A

C(out) = G(A,B) + P(A,B) . Cin
keep breaking down Cin into G and P functions
e.g. Cout = G4 + P4 . C3
=G4 + P4 . (G3 + P3 . C2) …etc

137
Q

gate delays for computing Cout in a carry look ahead and overall sum

A

3 gate delays: one for Pi, Gi, one for AND and one for OR

for overall sum, 4 gate delays

138
Q

4-bit CLA propagates if..

A

if all subsequent bits propagate

139
Q

4 bit CLA generates if…

A

if any bit generates and all subsequent bits propagate

140
Q

CLA adding n-bit numbers in constant gate delay

A

require order n^2 gates and order n inputs: impractical for large n

141
Q

more efficient CLA

A

chain 4 bit CLAs: carry ripples 4x faster

142
Q

a block is said to generate a carry if

A

it produces a carry independent of the carry in

143
Q

a block is said to propagate if

A

it produces a carry out whenever there is a carry in to the block

144
Q

instead of letting carry ripple through the CLA…

A

precompute whether a carry would be generated or propagated by each CLA

145
Q

4 bit CLA propagates if…

A

if all bits propagate, P = p4.p3.p2.p1

146
Q

4 bit CLA generates if…

A

any bit generates, and all subsequent bits propagate: G= g4 + p4.g3 + p4.p3.g2 + p4.p3.p2.g1

147
Q

each 4 bit block contains

A

a 4 bit ripple carry adder and some lookahead logic to compute the carry out given the carry in bit

148
Q

gate delay for 16 bit 2-level CLA

A

1 gate delay for bit level Gs and Ps
2 gate delays for block level Gs and Ps
1 gate delay for sums
2 gate delays for carries

149
Q

time order with 3 level CLA vs normal ripple adder

A 
CLA O(logn)
ripple adder O(n) (grows faster, more gates required = more gate delays)
150
Q

16 bit adders chained to give a gate delay of…

A

for an n bit adder: 2(n/16) + 4

151
Q

sequential circuits can be modelled as

A

finite state machines

152
Q

synchronous sequential circuits are made of

A

combinational components interleaved with banks of flip flops containing state of the circuit

153
Q

SR: NOR latch

A

bistable: two stable states for a given input
the S and R inputs are both usually 0. Pulse on S -> output = 1 (or remains 1). Pulse on R -> output = 0 (or remains 0).
output remains even when the pulse is over

154
Q

SR: NAND latch

A

bistable: two stable states for a given input
the S and R inputs are both usually 1. Pulse on S -> output = 0, Pulse on R -> output = 1
output remains even when the pulse is over

155
Q

D-latch

A

a latch separating what and when.
CLK: indicates when to change state
D: data input, indicates what the new input should be
when clock = 1, latch is transparent: data flows onto the output
when clock = 0, latch is opaque: output is constant

156
Q

register

A

bank of flip flops driven by the same clock

157
Q

enabled flip flop

A

flip flop with an additional input (an enable) controlling whether or not data is loaded into the register
can control input using multiplexor or control the clock = gated clock

158
Q

gated clocks issues

A

can cause glitches and timing errors

159
Q

number of transistors for a D-type flip flop

A

NOR/NAND = 4
NOT = 2
AND = NAND + NOT = 6
D-Flip flop = 46 . but by direct design = 20

160
Q

improved D latch

A

fewer gates = fewer transistors

Q = CLK . D + notCLK . Qprev

161
Q

issues with the improved D latch

A
  • race conditions: behaviour depends on which of the two routes carries the signal fastest and the gate delays
  • logically identical circuits may exhibit different behaviours depending on temperature and technicalities of gate construction
162
Q

problems caused by loops or cyclic paths. how to overcome this?

A
  • inserting registers into the cyclic paths: stores the state of the circuit and breaks the paths. synchronous with the clock, only update on an edge
  • if clock is sufficiently slow so all inputs to all the registers have settled, race conditions can’t arise
163
Q

synchronous sequential circuits consist of elements such that

A
  • every circuit element is either a register or combinational circuit
  • at least one element is a register
  • all registers receive the same clock signal
  • theres a register in every cyclic path
164
Q

a synchronous sequential circuit has

A
  • a discrete set of states {S0…Sk-1}
  • clock input, whose rising edge indicates when a state change occurs
  • functional specification detailing next state and all outputs for each possible current state and set of inputs
165
Q

dynamic discipline

A

restricts us to using circuit components satisfying time constraints allowing us to combine components

166
Q

t(setup)
t(hold)
t(ccq)
t(pcq)

A

t(setup): time before rising edge during which inputs must be stable
t(hold): time after rising edge during which inputs must be stable
t(ccq): time after rising edge until output starts to change
t(pcq): time after rising edge until output has stabilised

167
Q

how fast a computer operates is dependent on

A

clock frequency

168
Q

overclocking

A

setting the clock speed higher than the manufacturer recommends

169
Q

sequencing overhead

A

t(pcq) + t(setup)

this is normally fixed, along with the clock speed.

170
Q

clock speed ticks have to be at least…

A

min cycle time = t(pcq) + t(pd) + t(setup)
t(pd) time between last output stabilising and next input having stabilised
max clock freq = 1/ min cycle time in seconds

171
Q

elements of combinational logic must work within

A

bounds on t(pd) in order for the circuit to be reliable.

this is because clock and sequencing overhead is fixed

172
Q

t(hold) min delay requirement

A

t(ccq) + t(cd) > t(hold)
t(cd) > t(hold) - t(ccq)
t(cd) time between last output starting to change and next input starting to change
to allow direct connections of flip flops: often t(hold) < t(ccq) (no t(cd) if no CL element)

173
Q

hold time violations

A

find short path: if t(hold) > t(ccq) + t(cd) then input to flip flop may change before D value has reliably set its value to previous value

174
Q

fixing time hold violations

A

add buffers, so add another t(cd) until total(t(cd)) + t(ccq) > t(hold)

175
Q

metastable states: input D to a flip flop

A

If D is either 1/0 while the clock rises = stable state
if D changes state while clock is rising (between tsetup and thold) = metastable state = driven to 1/0 eventually but takes longer for state to stabilise

176
Q

synchronisers

A

two flip flops can synchronise the input with the clock- if input to a register is not synchronised with the clock the output may be indeterminate

177
Q

output of second register will be synchronised if..

A

resolution time of first register (time taken for output to stabilise) is small enough compared to clock rate

178
Q

pipelining

A

improves throughput at the expense of latency
inserting more registers into a circuit, decreasing clock cycle time/increasing clock frequency/increasing throughput
but not necessarily splits clock cycle time in half, as added sequence overhead and circuit can’t be divided exactly into two halves

179
Q

latency

A

number of clock cycles/overall time

Computer Systems (6 decks)

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