Lectures 1 and 2 - Introduction and Fundamentals

Question 0

Implementation or Microarchitecture

Answer 0

Logical organisation of the inner structure of the computer.

Question 1

Instruction Set Architecture

Answer 1

Defines the functional behaviour of the processor and hardware/software interface. It enables compatible implementations to be made that make different trade offs.

Question 2

Realisation

Answer 2

Physical structure embodying the implementation.

Question 3

Four major players in computer architecture arena

Answer 3

Applications, architectures, technology, markets

Question 4

Design goals and constraints are imposed by the ….

Answer 4

Target market, available technology and target applications.

Question 5

Important metrics

Answer 5

Energy (Joules)
Power (W)
Performance
Cost/Performance
Power Efficiency
Reliability (Mean Time to Failure)
Flexibility

Question 6

How were historic performance gains achieved?

Answer 6

Technology Scaling

Gates per clock

Instructions Per Cycle Increase

Instruction Count Decrease

Question 7

Technology Scaling Performance Improvement

Answer 7

Provides 1.4x transistor performance improvement per generation.

7 historic process generations provided a 10.5x performance improvement.

Question 8

Gates per clock performance improvement

Answer 8

Reduction from 100 to 10 gate delays so 10x performance improvement. 4x of this came from pipelining with an increase from 5 to 20 stages. 2.5x from circuit level advances e.g. new logic families.

Question 9

IPC and instruction count performance gain

Answer 9

~5-8x improvement in SPECint/MHz

Advances in compiler technology and impact of increased bus widths.

Question 10

VLSI technology scaling

Answer 10

Fabrication processes are characterised by feature sizes so improvements allow transistor and wire dimensions to be reduced. A linear reduction in transistor sizes enables quadratic increase in transistor count. Smaller transistors are also faster as resistance is independent and capacitance decreases with feature size.

Question 11

Porting a design to a new technology

Answer 11

Root 2 performance increased

Area reduced by a factor of 2

Dynamic power consumption reduced by half as capacitance scales by S and P=CV^2*f (as f increases by 1.4 to increase performance).

Question 12

Interconnect versus transistor scaling

Answer 12

Smaller transistor are faster/lower power but wires don’t scale in the same way. Resistance increases and capacitance per micron remains the same. Adding fat wires on upper levels can help mitigate this.

Question 13

Architectural Implications of poor wire scale

Answer 13

Can reach less state in a single clock cycle so decentralised structures work better. A bypass network between functional units may be preferable.

Question 14

Amdahl’s Law

Answer 14

Performance improvements are limited by the fraction of time the proposed enhancement can be employed.

Speed up = 1/((1-fraction_enhanced)+ (fraction_enhanced/speedup_enhanced))

Question 15

Law of diminishing returns

Answer 15

Incremental improvements in speedup gained by enhancing just a portion of the computation diminish as improvements are added.

Question 16

Are all enhancements worthwhile?

Answer 16

No, they consume design and implementation resources potentially slowing the common case. This may be indirectly by meaning less time is spent optimising the common case or directly by causing the cycle time to be extended.

Question 17

Typical program behaviour

Answer 17

Locality of reference - exploited by memory hierarchy

Predictable flow control - branch prediction exploits

Predictable data values - exploited at higher levels e.g. Memoization

Question 18

Principle of locality

Answer 18

Programs tend to resume data and instructions that they have used recently.

Question 19

Temporal locality

Answer 19

Recently accessed data are likely to be accessed again in the near future.

Question 20

Spatial locality

Answer 20

Accesses to nearby memory locations often occur close together in time.

Question 21

Locality in instruction reference stream

Answer 21

Temporal - loops and function calls

Spatial - instructions executed sequentially in absence of branch instructions. Many branches are to nearby instructions

Question 22

Locality in data reference stream

Answer 22

Temporal - Widely used program variables & the call stack.

Spatial - Access arrays sequentially, process streams, function calls and the stack frame

Question 23

CPU performance equation

Answer 23

1/performance = time/program = instructions/program x cycles/instruction x time/cycle

Question 24

Improving performance

Answer 24

Shorten clock cycle time - circuit design style/Microarchitecture CPI - Microarchitecture and ISA Instruction count - ISA and compiler technology

Question 25

Dynamic power

Answer 25

1/2 x Capacitative Load x voltage^2 x frequency switched

Question 26

Static power

Answer 26

Current-static x voltage

Question 27

Reducing power consumption

Answer 27

Reduce performance to save energy by scaling voltage/frequency. Reduce wastage by reducing superfluous switching with clock gating and operant isolation, by extracting and optimising the common-car and by power gating.

Question 28

Components of the ISA

Answer 28

Word size, operations, registers, operant types, addressing modes, instruction encodings, memory architecture, trap and interrupt architecture

Question 29

Changing ISAs in embedded processors

Answer 29

ISA has significant impact as area and cost constraints mean transistor budget and design budget are limit. Recompilation is not a big hurdle as many embedded devices may run one set of binaries for their life, they have short lifetimes and we want to squeeze as much as possible out of the compiler.

Question 30

How can we break link between applications and ISA?

Answer 30

JIT VM technologies such as .NET and the JVM Alternatively support conventional source ISA and translate at run time to target ISA.

Question 31

Problems with microcode controlling

Answer 31

Efficiently controlling a highly concurrent data path using microcode is complex. Handling exceptions in a pipelined CISC machine is complicated Microcode engine represents an unnecessary overhead especially when executing simple instructions

Question 32

RISC Design Goals

Answer 32

# Choose common instructions and addressing modes Target efficient pipelined implementation by ensuring instructions go through the same pipeline stages and executing them in a single cycle if possible. Assume use of high-level languages - the compiler optimises register usage and instruction schedule. Produce simple high-frequency implementation.

Question 33

Load-store architecture

Answer 33

Memory can only be accessed with load and store instructions. This permits simple fixed length instructions simplifying decoding. It also simplifies pipelining as instructions take a similar time to execute and memory is accessed at most once in one pipeline stage.

Question 34

Register calling conventions

Answer 34

Simple convention specifies temporary and saved registers. This gives both the caller and callee a chance to reduce unnecessary register spilling. Temporary registers aren't preserved by callee while callee saves saved registers.

Question 35

Register Windows

Answer 35

Register windows are used by some processors which improve performance of procedure call/return sequence by avoiding the need to explicitly spill registers to memory.

Question 36

Addressing modes

Answer 36

Register Immediate Register Indirect with displacement Register indirect

Question 37

Condition registers and flags

Answer 37

Options are condition codes, condition register and compare and branch. Trade-offs: Impact on local code scheduling optimisations Use of general purpose registers Number of instructions required to implement conditional branch Cycle time implications

Question 38

Encoding an instruction set

Answer 38

Balance: Number of registers supported Number of addressing modes supported Against: Size of instructions and compiled program Fetch and decoding logic complexity and pipeline complexity in general Options are: Variable length Fixed length Hybrid format

Question 39

16-bit instruction set extensions

Answer 39

Address a subset of operations, addressing modes and registers but allow for static code size reductions of 25-40%. They also have a 10-20% performance penalty.