Lecture 11 - Vector Processors

Question 1

Vector Registers

Answer 1

Each holds a fixed number of elements and has lots of ports so vector operations can be performed in parallel.

Question 2

Vector functional units

Answer 2

Fully pipelined so we can start processing a new vector element on each clock cycle.

Question 3

Vector load-store Unit

Answer 3

Data move between registers and memory at rate of one word per cycle.

Question 4

Scalar Registers

Answer 4

Provide data as input to vector functional units.

Question 5

Advantages of vector architectures

Answer 5

Exploit data-level parallelism to improve performance.

Potentially reduce complexity and reduce energy per operation because:

• Vector operations specify lots of independent operations which are simple to execute in parallel.
• Less switching activity in datapath.
• Drastic reduction in number of instructions.
• Regular patterns of access to register file and memory.

Question 6

Vector Datapath

Answer 6

Partition register file and functional units into multiple lanes as always operating on same element from different vectors.

Question 7

Initiation Rate

Answer 7

How many elemental operations are completed per cycle for each vector operation.

Question 8

Start-up time.

Answer 8

Time before first result. As functional units are pipelined, the first result will take pipeline depth clock cycles to be produced.

Question 9

Vector Length Register

Answer 9

Controls length of any vector operation.

Question 10

Strip Mining

Answer 10

Operate on odd-size piece of the vector size then complete MVL sized pieces until complete.

Question 11

Vector Stride

Answer 11

Need ability to read elements from memory separated by a fixed distance (stride). This only requires load/store unit to be modified.

Question 12

Chaining

Answer 12

Start next dependent instruction as soon as individual elements of source vectors become available. (Read-after-write hazards)

Question 13

Tailgating

Answer 13

Overwrite elements of one vector register as soon as they have been used by prior register. (Write-after-read hazards)

Question 14

Vector-mask Control

Answer 14

Use a boolean vector of length MVL to control execution of a vector instruction. The vector operation turns into no-op at elements where mask bit is clear.

Question 15

Scatter and Gather

Answer 15

Store and load vector indexed instructions to support loops which make indirect accesses to arrays.

Question 16

SIMD ISA Extensions

Answer 16

Add SIMD instructions to standard ISA by introducing new SIMD registers and functional units. This is done by supporting data parallel operations on wide registers e.g. treating 128-bit register as 8 16-bit values.

Question 17

Stream Processors

Answer 17

Organise application into streams and kernels. This a natural fit for many modern media-processing applications.