Lecture 16: Memory Management Flashcards
Memory Management Unit Responsibilities
-Another Resource Manager Component of the OS
- Memory Allocation:
responsible for allocating memory to processes - Address Mapping:
Necessary: 1) to run same code in different physical memory in different processes 2) to support process address space abstraction MMU responsible for mapping logical addresses generated by CPU instructions to physical addresses seen by memory controller
Logical Addresses
- An abstraction of memory
- memory referenced in assembly language instructions (e.g., BR X, LOAD R2,Y)
- starts at 0, contiguous
- reality: must be mapped to physical addresses (address mapping)
Logical Addresses Generated at:
- Compile-time
• relative addressing resolved here(e.g.:X,Y) - Link, load-time
• addresses dependent on external modules resolved here - Execution-time
• addresses generated by dynamic loading/linking resolved here
Logical Address Space
defined by base and limit registers
Base and Limit Registers: CPU
every physical memory access request must be between base and limit for that user
Generating Physical Addresses
• addresses used in MAR (memory address register)
• generated at runtime (execution time) by
memory management unit (MMU)
• above protocol enables dynamic program relocation (without having to modify program code)
Memory Allocation Goal 1: High Utilization
• ensure as much memory used as possible (minimize waste) (e.g.: want to use as much of street for street parking as
possible)
Memory Allocation Goal 2: High Concurrency
• support as many processes as possible
e.g.: cars exit when don’t require parking any more, so others can use
Memory Allocation Goal 3: Fast
-fast
Memory allocation: contiguous
-no gaps
Memory allocation: non-contiguous
-with gaps
Contiguous Pros and Cons
Pros:
- Easy implementation
- Easy to conceptualize
Cons:
-Poor memory utilization
Contiguous Types
- Fixed Partition allocation (parking lot)
2. Variable Partition allocation (side street parking)
Fixed Partition allocation (parking lot)
- Idea:
• divide memory a priori into fixed partitions (can vary in size) e.g.: parking lot: regular spaces, compact only, etc. - Allocation Policy:
• process P arrives needing k units of space:
choose partition (Ri) that is smallest but 3 k (best-fit) - Utilization Issue:
• internal fragmentation: parts of allocated partition unused - Implementation:
• requires limit and relocation registers
5.
•
In Practice: used in early batch systems:
1. knew memory needs of processes in advance
2. memory needs didn’t change much over process lifetime
Variable Partition allocation (side street parking)
-Idea: • allocate memory chunks as needed (analogous to side street parking) -best fit -worst fit -first-fit -next-fit
Variable Partition allocation policies
Allocation policies:
process P arrives needing k units of memory
a. Best-fit: choose hole that is smallest but ≥ k
b. Worst-fit: choose largest hole
c. First-fit; choose first hole with size ≥ k
d. Next-fit: choose next hole with size ≥ k
Fragmentation types
- External:
total memory exists to satisfy request, but not contiguous.
External fragragmentation can be periodically eliminated via compaction - Internal:
allocated memory may be > requested memory. Extra memory not used
Non-contiguous allocation
Idea:
Logical address space is partitioned, each partition mapping to a contiguous chunk of memory
Non-contiguous allocation: pros and cons (compared to contiguous)
Pros:
• better memory utilization
by dividing address space into smaller “chunks,” more
memory fragments can be used
Cons:
• more complex implementation (not just relocation & limit registers)
Non-contiguous schemes (3)
1. paging all chunks the same size (i.e.: chunks are physically determined) 2. segmentation chunks are variably sized (logically determined) 3. paged segmentation hybrid of (1) and (2)
Page Table Implementation
Every Process’ Page Table:
- kept in main memory
- location kept in process (special status) registers:
Page-table base register: (PTBR)
• location of page table for process
Page-table limit register: (PTLR)
• size of process page table
Caching
Use of high-speed memory to hold frequently accessed data
Associative Memory (TLB’s)
- Cache is faster than memory
2. Associative Memory permits parallel search
Issues with paging
Issue #1: Two memory accesses / logical address reference
Solution: TLB
Issue #2: Very large page tables
Solution: Page the page tables!! (Multilevel Paging)
