Instruction Set Architecture

Question 1

Address Space

Answer 1

Number of Drawers

Question 2

Addressability

Answer 2

number of bits per drawer

drawer width

Question 3

Decoder

Answer 3

Takes instruction apart (in case of LC 4, 16bit) and determines necessary control signals.
Translates instruction.
A Combinational logic block that computes control signals

Question 4

ISA

Answer 4

Instruction Set Architecture
Programmer-visible components and operations
- Everything needed to create a program for CPU
- Serves as ‘contract’ between programmer and CPU designer
- Different implementations of the same ISA are ‘binary compatible’

Question 5

ISA vs Microstructure

Answer 5

The ISA specifies the “interface” between the programs and the underlying computer hardware that must carry out the work for them. i.e. the ISA tells us what you can do with the computer, what operations it can perform, what data types, addressing modes etc. one can use with the particular computer.
Whereas the microstructure refers to the actual implementation, i.e. how this “interface” and the associated functionalities have been implemented under the hood.

Question 6

3 things specified by ISA / Basic components of ISA

Answer 6

1. Instruction set: defined by its set of opcodes, data types (acceptable representations of information such that ISA has opcodes that can operate on
   that representation -> ISA supports that data type), and addressing modes (mechanisms for specifying where the operands are located. Usually in memory, in a register or as part of the instruction)
2. Memory: how many locations, how many bits stored per location
3. Registers: how many, what size, how are they used

Question 7

OpCode

Answer 7

the portion of a machine language instruction that specifies the operation to be performed

Question 8

Processor Status Word Register (PSR)

Answer 8

16bit register where the lower 3 bits store the NZP bits. The PSR[15] stores the privilege level that the CPU is currently operating in.

Question 9

Program memory

Answer 9

where we store our instructions

Question 10

3 parts of NZP

Answer 10

1. NZP tester (3bits out)
   ■ Tests the output of the ALU for negative, zero, or positive
2. NZP register (3bits out, stored in the Processor Status-Word Register, bits [2:0])
   ■ Stores results of NZP tester (negative, zero, or positive)
   ■ NZP.WE = 1 for any instruction that writes to RegFile or PSR[15]
3. TEST (1 bit out) if condition is satisfied
   ■ Top input: I[11:9] (3bit user condition)
   ● Example: >= 0, <=0, etc.
   ■ Bottom input: the output of NZP (previous ALU’s value’s negative, zero, or positive)

Question 11

Binary Compatible

Answer 11

You can take same instructions, with same bits. You run it on 2 different CPUs, and while they might do things differently under the hood, the implementation is such that they will yield same result.

Question 12

Golden Rules of Branch Unit

Branch Unit = sets next PC value

Answer 12

1. Every instruction updates PC to PC+1 unless otherwise noted
2. NZP.WE = 1 for ANY instruction that writes to RegFile or PSR[15]
3. We have never ‘X’ for WE control signals

Question 13

Only instructions that can modify the privilege bit in PSR

Answer 13

TRAP and RTI

Question 14

LC 4 Memory

Answer 14

Adress Space = 2^16; 16bit address line
Addressability = 16bit
Memory partitioned into program and data memory

Question 15

LC 4 Registers

Answer 15

Register File: General Purpose Regisets
- 8 registers, each 16-bit wide
Program Counter: 16bit
Processor Status-Word Register: 16 bit
- contains NZP condition codes
-Not directly accessible, but used and affected by instructions

Question 16

Shift Arithmetic
Shift Logical
11010; 2 right

Answer 16

Logical: Zeros shifted into MSB
11010 -> 01101 ->00110

Arithmetic: MSB replicated on left, maintains 2C sign
11010 -> 11101 -> 11110

• > A Left Arithmetic Shift of one position moves each bit to the left by one. The vacant least significant bit (LSB) is filled with zero and the most significant bit (MSB) is discarded. It is identical to Left Logical Shift.
• > A Right Arithmetic Shift of one position moves each bit to the right by one. The least significant bit is discarded and the vacant MSB is filled with the value of the previous (now shifted one position to the right) MSB.

Question 17

Which compare instruction are useful in coding operation like: i>0, i<0 etc.

Answer 17

CMPI and CMPIU -> allow for immediate number to be included in instruction
But not CMP and CMPU

Question 18

Instruction that don’t modify the register file will not set the NZP bits?

Answer 18

Wrong, instructions might WRITE to reg file or set PSR[15] without modifying Reg file. Additionally, compare instructions do not impact reg file but still set NZP bits.

Question 19

How many cycles does LC4 need to execute one von Neumann loop

Answer 19

One Cycle. LC4 is a single cycle CPU

Question 20

What is advantage of separating Control Memory into Program Memory and Decoder

Answer 20

Before, whenever we added an new component the adressability of control memory was getting wider and wider
With splitting it into Program Memory and Decoder we can fix instruction length. We can add new control signals without changing instruction length.
Program Memory holds instruction without control signal data and
Decoder takes instruction apart and determines necessary control signals

Question 21

What CPU does during ADD

Answer 21

1. Do ALU calculation and store result: R1 = R2 + R3
2. Set NZP conditions codes: Figures out if ALU output is +, - or 0. Store result in Process Status Register
3. Increment PC

Question 22

What does it mean for a CPU to be “single cycle”?

Answer 22

All steps in Van Neumann Model are done in one step