IC Technologies Flashcards
What is noise immunity?
It is the ability of a circuit to be unaffected by noise
Why is noise a problem?
It induces a voltage which can render gate operation unpredictable
What are the two noise margins?
HIGH level
LOW level
Equation for High Level Noise Margin? VNH
VNH = VOH - VIH
VOH = minimum output HIGH voltage
VIH = minimum input HIGH voltage
Equation for LOW level noise margin? VNL
VNL = VIL - VOL
VIL = max input LOW voltage
VOL = max output LOW voltage
What is propagation delay?
Time taken for the signal to propagate from the input to the output
What are the two propagation delays to be aware of?
TPHL
TPLH
What is TPHL?
Time for signal to propagate from HIGH to LOW
What is TPLH?
Time for signal to propagate from LOW to HIGH
Equation for a 50% Duty Cycle
ICC = (ICCH + ICCL) /2
ICC = 50% duty cycle
ICCH = Current when gate output is HIGH
ICCL = Current when gate output is LOW
What is fanout?
The maximum amount of gates that can load the driving gate
What is the power dissipation like in a TTL and CMOS circuit?
In TTL, power dissipation is constant
In CMOS, power dissipation is linear but depends on frequency
Explain CMOS loading
A CMOS is a circuit that when the gate output is HIGH, charges the load gates. When gate output is LOW, the load gates discharge. The more load gates we add, the longer it takes to charge the load gates, and so the lower the frequency of operation. (Also lowers switching frequency)
Imagine the load gates like balloons, the more we add the longer it takes to fill them up since the driving gate can only fill these balloons at a certain rate. Think of the frequency as how many balloons it can fill up in a certain amount of time.
Explain TTL loading
TTL loading works with resistance, unlike CMOS that work with capacitance. Whenever the state is HIGH, the TTL delivers current to the load gates, the more load gates there are, the more current is had to provide. Eventually, the fan out limit is reached where the current being delivered is not high enough for the amount of load gates, and so the circuit’s is LOW. See how the circuit is becoming unpredictable now?
When the state is LOW, the TTL starts absorbing that current back in. The more loads gates there are, the more current it has to take in. The larger the current, the greater the potential difference will be. So if there are too many load gates / too much current, the voltage will spike too high to read LOW, and will cause the circuit’s state to reach HIGH.
The TTL circuit acts like a water faucet. In a HIGH state, it provides water to glasses (load gates). The more glasses there are, the more water is needed. In a LOW state it absorbs the water from the glasses back in. If there is too much water, the sink will overflow (like causing a HIGH).
So in a TTL circuit, what determines fanout capability?
The ability for the current to be absorbed.
Characteristics of MOSFETs? (CMOS transistors)
High input impedance (high resistance)
less noisy
Higher noise margins
Doesn’t experience thermal runaway
In a CMOS circuit with N and P channel transistors, when are they HIGH and LOW?
N channel:
HIGH when input is ON
LOW when input is OFF
P channel:
LOW when input is ON
HIGH when input is OFF
What are the 3 states of a tristate device?
HIGH
LOW
HIGH IMPEDANCE (HIGH Z)
