Digital Components - Latches And Flip Flops Flashcards
What are latches and how many stable states do they have?
Latches are simple memory cells because they can store the previous state. They have 2 stable states
What are the 4 states of a latch?
Usually the inputs are S and R. When S=1 and R=0, this means the outputs are SET. When R=1 and S=0, they are RESET
No change = The two or more inputs keep the latch producing the same outputs as initial
Reset = Q is LOW and Q’ is HIGH
Set = Q is HIGH and Q’ is LOW
Invalid = the outputs cannot be determined (Occurs when S and R are both 1)
*When the circuit is active LOW, Reset and Set are reversed. When R is 0, the circuits Resets. When S is 0, the circuits Sets
What is a gated SR latch?
An SR latch with a gate, also known as an Enabler. The S and R only affect the output when the EN is HIGH. The enabler is hence used as an input here
Problems with the gated SR latch?
At power up the initial state is unknown
When both inputs are a logic 1 we cannot determine what the outputs are
What is a gated D latch?
A latch with a gate (enabler) where on input is used, D, that is connect to inverters so that values 1,0 and 0,1 can be used. The Enabler is also used as an input here. The input D is only effective when EN is HIGH
What is a flip flop? What triggers a flip flop?
An edge triggered synchronous bistable device.
unlike latches, Flip flops are triggered by clocks
What is the main difference between a FlipFlop and a latch?
Latches are level triggered devices
Flip flops are edge triggered devices
What are the 3 types of flip flops and describe them briefly?
SR flip flop: Values of S and R are triggered upon the rising edge of the clock pulse
D type flip flops: Output Q is set to D upon the rising edge of the clock pulse
JK flip flops: An SR flip flop but instead the inputs of J and K are triggered on the falling edge of the clock pulse. This eliminates the problem of the invalid state
On the JK flip flop, the invalid state no longer exists as with the SR flip flops. What is the new state called?
Toggle.
Name a use of FFs?
Basic counters, they can store one memory
What are the two new pins in the JK flip flop?
PRESET: Q is set to logic 1
CLEAR: Q is set to logic 0
In a JK flip flop, where are the pins PRESET and CLEAR attached?
On either side of the flip flop.
What is the truth table for a JK flip flop?
J K Q Q’
0 0 Q Q’ No Change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q’ Q Toggle
What is the truth table for a JK FF with PRESET AND CLEAR?
P C Q
0 0 ? Indeterminate
0 1 1 Q is SET
1 0 0 Q is RESET
1 1 - Normal Operation
What is a single FF referred to?
A stage
A single flip flop only has two states, 0 and 1. How many states do 3 flip flops have? (Hint: 2^N)
8 states. 000, 001, 010, 011, 100, 101, 110, 111.
3 FFs can count up to 10
What are the 2 ways to connects FFs?
Synchronous: The FFs use the same clock pulse
Asynchronous: The FFs don’t use the same clock pulse
What does it mean when a FF’s clock pulse has the symbol > vs O>
> means the FF triggers on the rising edge of the clock pulse
O> means the FF triggers on the falling edge of the clock pulse
Describe the function of an Asynchronous 2 bit FF counter: See page 63 in booklet. Assume both FFs are RESET (both outputs Q0 and Q1 are set to 0.
- J and K are both HIGH and this doesn’t change
- At the first clock pulse, Q0 becomes 1. There is no clock pulse in the second FF as the clock input is 0. So Q1 has no change
- At the second clock pulse, Q0 becomes 0. There is now a clock pulse in the second FF as the clock input is 1. So Q1 changes to 1. This process keeps repeating and is known as TOGGLE.
Look at page 61. Having both J and K HIGH, causes the output Q and Q’ to keep changing after each clock pulse after the initial one.
Name a use for FFs?
Digital Divider, but you need a 3 bit asynchronous counter for this. See page 63
Explain the propagation delay in any multi bit asynchronous FF
In a 3 bit FF, there are 3 time delays between the clock pulse and the final state of the 3 FFs.
This delay limits the rate at which the counter can clock, causing decoding problems
Explain how in a synchronous 2 bit FF we can use the propagation delay to our advantage? See page 65
- Set both FFs to RESET
- In the first clock pulse, Q0 is 1, but due to the propagation delay, the J and K input of the second flip flop is still 0 and so Q1 is 0 (no change). Thus, the clock reads 0 1 (1 second)
- In the second clock pulse, Q0 is 0, but due to the propagation delay, the J and K input of the second flip flip is now 1 and so Q1 is 1 (change). Thus, the clock reads 1 0 (2 seconds)
- In the third clock pulse, Q0 is 1, but due to the propagation delay, the J and K input of the second flip flip is now 0 and so Q1 is 1 (no change). Thus, the clock reads 1 1 (3 seconds).
What are the advantages of the Synchronous 2 bit counter FF
The propagation delay is not cumulative unlike in the asynchronous counters.
Works better in complex high frequency systems
